集成电路设计

随着半导体工艺的飞速发展，SoC设计技术已经成为集成电路设计的主流技术。

With the rapidly development of semiconductor process technology , SoC design has become a predominant paradigm in IC design industry today .

通过利用VHDL设计UART的IP核说明了IP核或者大型设计的流程以及IP核设计在以后的集成电路设计中的重要性。

The importance of IP kernel or large - scale design flow and IP kernel design in the latter IC design is described by designing UART IP kernel via VHDL .

集成电路设计方法及IP设计技术的研究

Research on the Methodology of IC Design and Technology of IP Design

基于CMOS工艺的中小规模数字集成电路设计浅析

Designing of Middle Scale Digital Integrated Circuit Based on CMOS Technology

硅栅等平面CMOS集成电路设计规则的研究及应用

An Investigation and application of Si-gate LOCOS CMOS Design Rules

在深亚微米、超深亚微米工艺水平下的超大规模集成电路设计需要高性能的EDA（电子设计自动化，ElectricalDesignAutomation）软件的支持。

High performance EDA ( electrical design automation ) software environment is needed in the VLSI design under deep-submicron and very-deep-submicron technology .

在货物装载、木材下料、超大规模集成电路设计等工作中提出了矩形packing问题。

The rectangle-packing problem often appears in loading , timber cutting , very large scale integration design , etc.

在CMOS射频集成电路设计中对稳定性的分析

The Stability Analysis in CMOS RFIC Design

在模拟集成电路设计中，关于X轴和Y轴同时对称的Stack，以及模块之间的合并，对于增加器件之间的匹配和控制寄生是至关重要的。

In analog VLSI design , 2-dimensional symmetry stack and block merging are critical for mismatch minimization and parasitic control .

本文使用专用集成电路设计了1Wire总线与PC机USB接口转换器。

In this paper , an adaptor between 1-Wire bus and USB interface in PC using special-purpose IC is designed .

象其它的集成电路设计技术一样，光刻分辨率增强技术也需要基于计算机技术的EDA工具的支持。

Like other technologies used in IC design , RET needs the support of computer technology .

SoC设计是以IP核复用为基础的，基于IP核模块的大规模集成电路设计是硬件实现的关键。

SoC design is based on IP reuse , and large scale integrated circuit design based on IP core is the key of hardware implementation .

整个数字ASIC流程的实现体现了数字集成电路设计的普遍实现方法。

The realization of the whole digital ASIC flow represents the common methods of digital IC design .

基于IP可重用方法学的SoC设计理论和技术的起步与飞速发展，标志着集成电路设计已进入片上系统（SoC）时代。

The fast development of SoC design theory and technology based on IP reuse methodology indicates that integrated circuits has entered into System-on-Chip era .

文中分析了深亚微米集成电路设计中对两相邻耦合RC互连串扰的成因，论述了在设计中抑制串扰一般方法。

This paper presents the causes of crosstalk between tow neighboring coupled RC interconnects in submicron integrated circuit design and discusses its control .

本文的研究内容包括两部分：MOS器件模型参数提取和高速数字集成电路设计。

MOS device parameter extraction and high speed digital IC design are the two main tasks of this paper .

随着电子设计自动化（EDA）的发展，IP设计已成为大规模集成电路设计的方向。

With the development of electronic design automation ( EDA ), IP design has become the futuristic trend for the designing of large-scale integrated circuits .

SAT问题在人工智能、软件工程、VLSI集成电路设计领域具有广泛的应用。

SAT is an important issue in computer science and artificial intelligence and has a wide applications in software engineering , VLSI integrated circuit design .

片上网络（NetworkOnChip，NoC）是应对超大规模集成电路设计中由尺寸和通信需求等因素带来的诸多问题的一种全新方案。

NoC ( Network on Chip ) is a new solution to the problems caused by the size of chip and on-chip communication demands in very-large scale integrated circuit design .

随着系统规模的不断扩大、系统复杂度的不断提高、IP核数量的不断增长，集成电路设计面临更多的难题。

With the continuous expansion of the system size , the continuous improvement of the system complexity and the growing number of IP core , integrated circuit design is facing more problems .

在CMOS集成电路设计技术和应用技术中，低功耗设计是一个十分重要的研究内容。

With the development of the design and application technology of CMOS integrated circuits , low power design is one of the most important research issues .

无线通信技术和CMOS工艺的迅猛发展使得基于CMOS工艺的射频集成电路设计成为当前研究的热点。

Due to the rapid development in wireless communication and the CMOS technology , the research of RFIC based on CMOS technology becomes hot point now .

FPGA（现场可编程门阵列）芯片是IC领域的重要组成部分，越来越多的集成电路设计和仿真依靠其来完成。

FPGA ( Field Programmable Gate Array ) chip is an important part of IC industry products . More and more IC designs and simulations are implemented using FPGA .

介绍了集成电路设计中ESD保护的基本原理和几种常用的保护方法并比较其优劣。

The basic ESD protection theory in IC design , the normal protection structure and the advantage or disadvantage are introduced .

可满足性问题（SAT问题）在数理逻辑、人工智能、机器学习、约束满足问题、VLSI集成电路设计与检测以及计算机科学理论等领域具有广阔的应用背景。

The satisfiable ( SAT ) problem plays an important role in artificial intelligence , machine learning , mathematical logic , VLSI design and detection other areas .

在现状分析的基础上，全面论述了加入WTO对我国集成电路设计业的影响以及建议政府和企业可采取的应对策略。

Based on the analysis of the status of the industry , the impact on nation 's IC design industry after entering WTO is discussed in this paper , as well as corresponding measures .

面对市场中不断缩短的产品开发周期和深亚微米的制造工艺要求，SOC设计方法学已经成为集成电路设计工业最好的解决办法。

When IC designer faces the pressure of Time to Market and the need of deep submicron fabricate technology , a new design methodology need be found .

随着通信网络技术和集成电路设计的高速发展，分布式嵌入式（DistributedEmbedded，DE）系统向大规模复杂异构的方向发展。

With the rapid development of communication network technology and integrated circuit design , distributed embedded ( Distributed Embedded , DE ) systems has being developed to the direction of large-scale , complex and heterogeneous .

一个成功流片的锁相环（PLL）型频率综合器范例，被引入非微电子专业学员集成电路设计教学中。

A successfully fabricated PLL synthesizer is applied to class teaching of IC design for non-microelectronics major students .

JTAG是一种重要的调试架构，已被电子电器工程师协会收录并作为集成电路设计标准，被命名为IEEEstd。

JTAG is a important type of debug architectures , which has been registered as one of IC designing specifications named IEEE Std.