边沿触发器

一种单锁存器CMOS三值D型边沿触发器设计

CMOS Ternary D-Type Edge-triggered Flip-Flop Using One Latch

TTLJK边沿触发器在CP脉冲边沿会出现输出状态异变现象。

When TTL JK edge-triggered flip-flop is in rise and fall edges of CP , its output state should arise abnormal changes .

新型电流型CMOS四值边沿触发器设计

Novel current-mode CMOS quaternary edge-triggered flip-flops

提出了一种只使用单个锁存器的CMOS三值D型边沿触发器设计。

A novel CMOS ternary D type edge triggered flip flop using a single latch is presented .

在二值单闩锁结构边沿触发器的基础上，把利用时钟信号竞争冒险的思想应用于三值电路中，提出了基于CMOS传输门的二值D型时钟信号竞争型边沿触发器。

Then this principle is adopted in ternary circuit , a new ternary D type edge-triggered flip-fiop based on CMOS transmission gate is proposed .

时钟信号竞争型边沿触发器

Edge-Triggered FliP-Elops Based on Clock Signal Racing

三值边沿触发器的研究

On ternary edge - triggered flip-flop

在传统触发器结构的基础上，本文提出了单闩锁结构边沿触发器设计，它通过利用时钟信号的竞争冒险产生窄脉冲控制单一锁存器以实现触发器的一次状态转换功能。

Based on the construction of traditional flip-flop , we propose a novel edge-triggered flip-flip using one latch controlled by narrow pulse according to race-hazard of clock .

由D触发器改进的边沿JK触发器

Edge-triggered JK flip-flop Improved from D flip-flop

介绍了两种已有的主从型边沿D触发器，它们具有很强的抗单粒子翻转能力。

Two typical master-slave type D flip-flop of strong hardness to Single Event Upset ( SEU ) for radiation environment are introduced .

在对抗单粒子效应技术研究的基础上，构造了一种改进型的抗单粒子翻转和单粒子瞬变的主从型边沿D触发器。

Based on SEU , SET mitigation techniques , an improved D flip flop which can be used for SEE mitigation was proposed .

谈主从式J-K触发器与边沿式J-K触发器的区别

Talking about the Differences between Master-slaver Mode J-K Flip-flop and Edge J-K Flip-flop

从概念到时序图等几个方面介绍了主从式J-K触发器与边沿式J-K触发器的主要区别，并分析了两者在何种特定的工作条件下，功能才会相同。

This paper introduces the main differences between the master-slaver mode J-K flip-flop and the edge J-K flip-flop from aspects of the concept , and sequence diagrams , etc. , and analyzes on that under what kind of special working condition , the two flip-flops will have the identical function .

提出了一种基于共振隧穿二极管的新型边沿触发D触发器并将之用于构成二进制分频器。

A novel edge-triggered D-flip-flop based on a resonant tunneling diode ( RTD ) is proposed and used to construct a binary frequency divider .

短的CP边沿时间，是触发器正常工作的重要条件之一。

The short CP edge 's time is one of the important conditions for the normal usage of flip-flops .