异或门

基于异或门的组合逻辑化简CAD

Function Minimization of Combinational Logic Cad Based on XOR Gate The Door

本文对一种用ECL异或门实现高速QPSK的系统工作原理和伪码QPSK调制的功率谱进行理论分析和实验研究。

The theoretical analysis and experimental research of The principles of QPSK with ECL XOR gates and the power spectra of PN code modulated QPSK waves are done .

基于SOA辅助的全光逻辑异或门性能研究

Research on the Performance of All Optical XOR Gate based on SOA-Assisted

N（23,12）是一个异步的组合逻辑电路，能用12个大数逻辑门和77个异或门电路来实现。

N ( 23,12 ) is an asynchronous combinational logic circuit which can be implemented with 12 majestic-logic gates and 77 exclusive-OR gates .

与SOAMZI异或门相比，LOAMZI异或门输出信号的消光比较高，功率较低；

The output signals of LOA-MZI have higher extinction ratio and lower power compared with SOA-MZI ;

介绍了目前几种基于SOA的逻辑异或门的实现方法，并以TOAD结构为实验方案，从理论上推导TOAD实现全光异或逻辑的条件。

Introduce the methods of all optical XOR based SOA , and deduce the condition to realize all optical XOR using TOAD . 4 .

首先介绍了基于异或门的相位差测量方法和基于近似直线的相位差测量方法，然后介绍了两种基于DSP的测量方法。

This paper discusses two measurement methods for the phase shift measurement , one is based on the exclusive-or gate , the other is based on the approximate straight-line ; then introduces two measurement methods based on DSP .

与传统的半导体光放大器（SOA）构成的马赫曾德尔干涉仪型异或门进行了比较，从器件结构上对两种异或门运算结果的差异给出了解释。

The performance of the XOR result has been analyzed and compared with the semiconductor optical amplifier ( SOA ) - MZI . The result differences of the two XOR gates are explained from the structural property .

本文结合二进制数字PSK信号和异或门的特点，组成了一个十分简单的异或门二进制PSK。

Basing on the properties of binary digital PSK and exclusive-OR gate , this paper gives a quite simple exclusive-OR gate for binary PSK .

通过查找钱氏搜索电路中GF（Galoisfield）常数乘法器的公共模2加运算并进行预运算，GOA能够有效地减少电路中异或门的数量，从而减少电路面积。

By finding out the common modulo 2 additions within groups of Galois field ( GF ) multipliers and pre-computing the common items , the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area .

通过分析，认为起主要作用的是CLK频率和异或门检相带来的误差，在最佳CLK频率，两项之和近达±1%FS。

The main errors above are CLK frequency and XOR gate phase detection . At the best frequency , the sum of the two errors is nearly ± 1 % FS .

研究了基于载流子速率方程的半导体光放大器分段数值模型和SOA的非简并四波混频效应，在此基础上提出了三输入的RZ/NZR-DPSK格式数据逻辑异或门和RZ-OOK格式逻辑与门方案。

The numerical model of semiconductor optical amplifier based on the carrier rate equation and non-degenerate four-wave mixing effect of SOA are studied , and the multi-input RZ / NRZ-DPSK format data logic XOR gate and RZ-OOK format logic AND gate are put forward .

利用该性质，提出了一个新的串行正规基乘法器，该乘法器要求（2m-2）个二值输入的异或门，m个二值输入的与门。

Using these properties , a new II-type optimal normal basis serial multiplier is proposed , which needs ( 2m-2 ) XOR gates and m AND gates .

该方案无需重新配置系统的参数，仅改变输入信号即可实现两输入或三输入的RZ/NRZ-DPSK格式逻辑异或门和RZ-OOK格式逻辑与门。

In the proposed scheme , it does not need to reconfigure the parameters of the system , only change the input signal , two or three input DPSK format logic XOR gate and RZ-OOK format logic AND gate can be realized .

异或门低功耗优化展开方法

A Novel Optimization Approach for Low Power XOR Gate Decomposition

逻辑设计的一种新方法&以异或门为基础的逻辑设计

A new way of logic design & logic design based on exclusive-OR gate

输入信号的占空比对异或门混频器差频输出的影响

Influence of input duty cycle on difference frequency performance based on XOR gate mixer

一种用异或门及D触发器组成的0～±180°相位差测量电路，能够测量两个同频率的交流量的相位差及其相位关系。

A kind of phase difference measure circuit which is composed exclusive or gate and D-flip-flop .

改进异或门拓扑结构实现的二倍频器，结构简单、实用，降低了电路复杂度。

The clock signal is obtained by using a frequency doubler which uses a modified XOR topology , so that the complexity of the system is reduced .

介绍一种以异或门和电压比较器为核心器件的具有温度补偿的接近传感器电路。阐述了该电路的工作原理

Introduces the circuit of a proximity sensor with temperature compensation The core components of the sensor are two voltage comparators and a exclusive-or gate The principle of the circuit is described in detail

对该种换位盒的空间复杂度和时间复杂度分别用硬件中异或门的数目和比特流穿越异或门的层数加以了度量。

The space complexity and the time complexity of the P-boxes are measured by the number of exclusive-OR gates in the hardware and the layer number of bit stream passing through exclusive-OR gates separately .

增加控制脉冲，可以提高逻辑异或门的性能，但同时，控制脉冲功率的增加也会使输出信号恶化，因此需要合理选择控制脉冲的功率。

In addition , the performance of XOR logic gate can be improved by additional control pulse . However , the increase of control pulse power would deteriorate the output signal , and then the control pulse power should be chosen properly .

提出井阐述了以异或门为基础的组合逻辑电路的设计原理和设计方法，结合具体实例，指明了谊方法的适用范围，以及在优化逻辑设计、提高电路性能方面的优越性。

This paper presented and expounded the principle and way of design in combinational logic circuit based on exclusive-OR gate , pointed out the applicability of this way and the superiority in the optimization of logic design and improvement of circuit function in combination with concrete living examples .