寄存器电路

自激移位寄存器电路

Autonomous shift register circuit

移位寄存型向量寄存器电路

A vector register circuit of shift register mode

提出一种互补结构的寄存器电路设计方案，用于减小DES加密电路的差分功率信号，防御差分功耗分析。

A complement register structure is proposed for a DES circuit . The structure can reduce the differential power signal of a DES circuit and lead to the failure of differential power analysis .

提出一种低功耗准动态移位寄存器电路，这种电路静态功耗几乎为0，仅仅存在动态功耗；

In this paper a new low-power quasi-dynamic shift register is presented . It is of low power dissipation near to 0 for the static power and has only dynamic power .

应用MSI移位寄存器设计时序电路的新方法

Sequential Circuit Design Using MSI Shift Register

接着，针对生成矩阵的准循环特性，提出了一种新的基于反馈移位寄存器的编码电路，并用FPGA进行了实现。再次，论文对译码算法和译码器实现进行了研究。

Next , according to the characteristics of quasi-cyclic matrix , a new encoding circuit using feedback shift registers is proposed and implemented by FPGA . Thirdly , the decoding algorithm and decoder implementation are studied .

首先，在软件变异测试的基础上，针对Veriloghdl描述的寄存器传输级电路，提出一种运用于数字集成电路功能验证的变异测试方法。

First of all , based on software mutation testing , a new hardware mutation testing approach is proposed to evaluate digital integrated circuit functional verification . This approach applies to such a kind of circuit described in Verilog HDL .

HM-hash以并行线性反馈移位寄存器作为基本电路，采用并行压缩方式计算哈希值，利用压缩过程的信息损失而带来的单向性提供哈希函数的安全性。

Taking parallel LFSR as the basic component HM-hash provides the security of hash function using one-wayness brought by the information loss in the process of compression .

基于移位寄存器的监控电路在油气悬架试验系统中的应用

Application of a Monitoring Circuit Based on Shift Register in the Hydro-pneumatic Testing System

移位寄存器式存储电路

Shift register storage circuit

系统设计了A16/D16寄存器基接口电路，开发了软面板和仪器驱动程序。

The method to achieve circuit of A16 / D16 register-based interface is put forward , the softpanel and drivers to apparatus are developed .

基于USB接口的VXI寄存器基模块控制电路设计

The Design of VXI Register-based Module Control Circuit Based on USB Interface

串行编码电路采用移位寄存器实现，并行电路由一个组合逻辑网络和余数寄存器构成。

The serial encoder is designed with shift registers , the parallel encoder is consisted of a combinational logic network and remainder registers .