寄存器组

为了减少寄存器堆的读写端口个数，进而提高寄存器的访问速度，有的处理器要求所有二元操作指令的两个源操作数必须来自不同的寄存器组。

We know that the access speed of a register file is inversely proportional to its port number .

重点介绍了S3ViRGE/DX寄存器组、软件结构、PCI接口的应用、硬件图形加速和显卡时钟。

What described mainly in this paper are registers of S3 ViRGE / DX , structure of the software , PCI , hardware graphies acceleration and the chip clocks .

SOC应用中寄存器组设计的自动化

The Automated Design of Register Set Used in SOC

VGA寄存器组的操作安全性内部自查有效防范操作风险

Study of the Security for Operating the VGA Registers The inside check against the risk of operating effectively

通过采用调试接口电路的流水线映像寄存器组和特殊数据通路，可以避免在CPU关键路径上插入扫描链实现“非侵入性”的调试功能。

By using pipeline shadow registers and special data path in debug interface circuit , scan chain is no longer needed to insert in the critical path of CPU to facilitate non-intrusive debug capability .

在发送数据前，加密卡与主机要进行密钥交互，交互数据传输包括寄存器组传输和DMA传输两种方式。

Before the data sending , the encryption card gets the key from the PC in the two following manners : the register group transmission and the DMA transmission .

介绍了片上系统（SOC）技术在航空电子中应用的实例，重点讨论了在设备寄存器组设计中如何自动生成VHDL的源文件。

In this paper the example of SOC design technology applied in the avionics system is introduced , with focus on how to produce source files of VHDL automatically for instrument register set design .

本文首先介绍HIPP芯片的体系结构、数据处理模型和会话的概念，在此基础上重点介绍了DPU，包括其工作环境、代码、寄存器组、指令集、标记；

This paper firstly have a instruction on the HIPP architecture , packet process modal and the concept of session , based on which is the emphasis DPU , including DPU environment , code , register set , instruction set , token .

多寄存器组网络处理器上的寄存器分配技术

Register Allocation on Network Processors with Multiple Register Banks

提出了一种相连多寄存器组结构上的寄存器分配方法。

Propose a register allocation framework for machines with connected and partitioned register banks .

在快捷菜单上，选择要显示或隐藏的寄存器组。

On the shortcut menu , select the register groups you want to show or hide .

该算法通过对半字节比较器的比较结果和延时寄存器组的共享，极大地提高了资源的利用率。

This algorithm shares the result of half byte comparator and delay register array , improved resource utilization ratio extremely .

在嵌入式系统中，共享的资源典型的有内存块或寄存器组。

In embedded systems , the shared resource is typically a block of memory , a global variable , or a set of registers .

至少一个寄存器组专门用于特定类的线程，并且不能为其它线程所使用，即使在闲置时也是如此。

At least one of the register sets is dedicated for use by a special class of threads , and can not be used by other threads even if idle .

我们通过提出寄存器组划分图的概念以及对它相应的建立、化简和分裂方法，解决了上述问题。

In this thesis , the concept of register bank partition graph is introduced . Then we show how to attack these problems by building , simplify and split the graph . 2 .

论文分析了处理器内部部件的工作原理，详细阐述了微处理器的取指单元、译码单元、执行单元、寄存器组和控制核心的设计。

The work principle of every part of microprocessor is analyzed , and a strong emphasis is laid on the design of program counter , instructions decipher , execute unit , register group and control center .

在队列寄存器组中将传输请求分为读请求和写请求，分别由读传输状态机和写传输状态机控制执行。

In the queue registers , every transfer request is subdivided into read requests and write requests . Read requests are controlled by read transfer state machine , write requests are controlled by write transfer state machine .

本文对相连多寄存器组体系结构上的寄存器分配关键技术进行了研究。

We have studied the register allocation problems on this kind of processors . The work described in this thesis has following contributions : 1 . Propose a register allocation framework for machines with connected and partitioned register banks .

在引入特殊的数据存储格式和状态信息寄存器组的基础上，提出一种高效的存储器管理方法，简化了编解码过程，实现了数据处理的流水线操作，也大大减少了对存储器的读写次数。

By adopting special memory format and state information registers , an efficient memory organization method is presented , whose main characteristics include the simplification of the coding-decoding , pipelined data processing , and a significant reduction of read-write memory accesses .

但在相连寄存器组结构的处理器上，各寄存器组字长相同并有数据通路相连，能存放相同的数据，指令的操作数可来自多个寄存器组。

But for those processors with connected and partitioned register banks , each bank is in the same word-length and can hold the same value . In such way , operands of an instruction can be placed in multiple register banks .

使用存储器操作指示寄存器、分层寄存器组，能够简化子程序调用方式。

The chip use memory indicating register and lever register group , which can simplify sub & program calling method .

它有3种分配方式可供灵活使用：单个寄存器、流水寄存器和寄存器组方式。

Three allocation styles are designed for flexible application : single , pipeline and groupe register styles .

消息基器件不仅具有基本配置寄存器，还拥有通讯寄存器组并支持字串行通信协议。

The message-based device has not only the basic configuration register , but also communication register and supports word serial communication protocols .