流水线技术

流水线技术在基于FPGA的DSP运算中的应用研究

Research on Application of Pipeline Technology Based on FPGA in DSP Operation

流水线技术在LMS算法硬件实现中的应用

Application of pipeline technique in realization of LMS algorithm

多线程Web服务器设计中的流水线技术

Pipelining Technology in the Design of Multi Thread Web Server

变频器控制系统FPGA设计中分层多级流水线技术

Pipeline Optimization Technology of Inventer ′ s Control System based on FPGA

应用流水线技术设计DDS专用集成电路

ASIC of DDS designed with pipeline technique

文章基于FPGA采用流水线技术和优化设计，提出了一种更高效的AES算法IP核的设计方法。

This paper presents an efficient design of AES algorithm 's IP core in FPGA using pipelining technique and optimized methods .

再利用DSP的硬件乘法和软件流水线技术，对译码过程进行优化，从而使该译码算法得以快速实现。

The hardware multiplication and software pipelining loops of DSP are utilized to optimize the decoding process . The fast decoding is realized consequently .

现代RISC处理器的流水线技术

Pip ( ? ) line Technology of Modern RISC Processors

在PLD设计中使用流水线技术，能够提高系统速度。

As use the principle on PLD design , the system velocity raised able .

本文介绍流水线技术在超大规模集成电路FPGA和CPLD设计中的应用，文中对给出的例子进行了仿真，并给出了比较结果。

This paper discusses the application of pipeline technique which is used in very large scale integrated circuit such as FPGA and CPLD .

实际应用表明，指令控制流水线技术能够有效降低EPIC微处理器的设计复杂度。

The practical application shows that the instruction pipeline can decrease the designing complexity of the EPIC microprocessor effectively .

MIPS的流水线技术和基于流水线的乘法器设计

MIPS Pipeline Technology and Multiplier Design Based on Pipeline

结果表明，整个设计方案利用FPGA实现了硬件并行和流水线技术，保证了视频的实时处理。

Benefit from the hardware parallelism and pipeline technology of FPGA , the experimental results show that the performance of real-time processing for the video is entirely achieved .

随着超大规模可编程器件FPGACPLD和流水线技术的迅速发展，使得高速DSP运算的快速编程实现成为了可能。

With the rapid development of VLSI programmable device such as FPGA / CPLD and assembly-line technique , the fast programmable design method of high-speed DSP becomes possible .

分布式算法设计分数延迟FIR滤波器是将乘法运算转换为查找表操作并结合流水线技术节省硬件资源，提升处理速度。

Multiplication operation is transformed to look-up table operation and combining with pipelining technology to reduce hardware resources using and improve processing speed , based on distributed arithmetic .

信号分解基于矢量信号直角坐标的原理，运用DSP技术实现，并且采用信号归一化、查找表和流水线技术以增大系统处理速度和吞吐量。

The signal decomposition is based on the principle of rectangular coordinates of vector signals , realized using DSP techniques using signal normalized , look-up tables and pipelining techniques to increase system processing speed and throughput .

介绍了基于流水线技术的cache原理.并利用它的基本原理和技术，提出了设计指令cache关键技术和方法。

This paper introduces the principle of Cache , which is based on pipeline process technology , and how to apply its principle and technology to designing instruction Cache on the based of pipeline .

引入流水线技术，采用可编程门阵列（FPGA），基于超高速集成电路硬件描述语言（VHDL）来实现数据的加解密。

Introduce production line technology , employ Field-Programmable Gate Array ( FPGA ) and use Very-High-Speed Integrated Circuit Hardware Description Language ( VHDL ) to realize data encryption and deciphering . 3 .

为了改善电路的性能，在设计中不仅采用了双通道和流水线技术，而且结合FPGA芯片的结构特点，采用了许多针对性的电路，并充分使用了FPGA上的DSP运算模块。

In order to improve the performance , double data channels and pipelining technology were adopted in the design . And many special circuits and DSP blocks of FPGA were used fully according to the feature of FPGA chips .

在此体系中，块存储器以对角存储的方式被划分为八块双口SRAM，一维离散小波运算单元采用流水线技术设计。

In this architecture , a tile memory is divided into 8 dual-port SRAM arranged in diagonal storage mode and 1-D DWT unit is designed by pipeline technique .

后对数据处理单元进行了设计，利用流水线技术实现了AES算法，解决了ATA协议和AES算法数据宽度不一致等问题。

After the data-processing module has been designed , the use of pipelining technology AES algorithm to solve the ATA agreement and AES algorithm width data inconsistencies , and other issues .

在插值滤波器的Farrow实现结构基础上，融入了流水线技术和并行处理技术，提出了一种新的实现结构。

A new structure bases on the Farrow structure of interpolation filter is proposed by pipelining and Parallel processing technology .

在此基础上，设计了RSA密码芯片的总体方案和系统结构；阐述了运用三级流水线技术，实现高速并行RSA算法硬件的设计技术和方法；

And , give the total design scheme and system structure of RSA cryptogram chip , expound the design technology and method of high speed parallel RSA arithmetic hardware using three steps pipeline technology .

Nios是基于RISC、流水线技术的通用嵌入式处理器软内核，它是整个系统的中枢。

Nios is based on RISC technology ; it is a soft core of common embedded processor which adopts the pipelined technology and a centre of the whole system .

DSP芯片存储系统采用了哈佛结构，并使用多级流水线技术，以其强大的数据处理功能在通信和信号处理等领域得到了广泛应用，成为研究的热点。

The Structure of the DSP chips is Harvard . DSP are getting more and more attentions in the information field , due to its powerful signal processing ability , which is becoming a hotspot in communication and other correlative signal processing fields .

论文探讨了RS解码器中广泛使用的改进的欧氏算法（ME）的实现，利用流水线技术和复用有限域乘法器的方法设计了一种低复杂度的ME算法实现结构。

This thesis investigated the implementation of the modified Euclidean ( ME ) algorithm which was extensively used in RS decoder and proposed a low complexity structure of ME algorithm by using pipelining technique and multiplexing finite field multiplier .

包括利用FPGA实现数字延时的关键技术，涉及到对系数的处理和误差分析，分布式算法和流水线技术，并以FPGA的IP核的方式实现了分数延时滤波器。

This study is about the key technologies of using FPGA to implement digital delay , related to the coefficient processing and error analysis , distributed algorithm and pipeline technology . Then the fractional delay filter is implemented by means of FPGA IP core .

利用FPGA在硬件上实现了该算法，内部采用流水线技术，校正系数存储在FPGA的片内存储器中并实现了盲元补偿。

Moreover , the algorithm is implemented on the hardware structure of FPGA . In the FPGA design , the pipelined technique is applied and the correction coefficient is stored in the interior memory of FPGA , meanwhile , blind pixel compensation is implemented .

该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。

To erase the bootless power dissipation of the redundant leap of the clock , this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique .

随后，又将流水线技术应用于该算法，对该方法进行改进，完成了基于流水线技术的BCD码除法运算的设计，并用此方法实现了频率特性的测试。

And with the pipeline technology applied in it , the arithmetic is improved . Furthermore , it is applied in the design of the frequency character test module .