总线仲裁

总线仲裁及通信协议由FPGA编程实现。

Within FPGA bus arbitration and communication protocol are realized .

基于FPGA的PCI总线仲裁器设计

Design of PCI Bus Arbitration Device Based on FPGA

PCI总线仲裁逻辑及其在嵌入式设备中的应用

Arbiter Logic of PCI Bus and Application in the Embedded Device

基于CPLD的多单片机总线仲裁的设计与实现

Design and implementation of multi-single-chip computers interconnection organization based on CPLD

用CPLD实现PCI总线仲裁器

Implementation of PCI bus arbiter using CPLD

PCI总线仲裁器的设计及实现

Design and Realization of PCI Arbiter

详细介绍了利用大规模FPGA芯片实现系统总线仲裁和逻辑控制的设计思想；

It also introduces in detail the design thought of realizing system bus arbitration and logical control by largescale FPGA chip .

在GPIB－VX1控制S模块中，CPU和接口芯片的本地总线仲裁机制不同，文中分别对其加以讨论，提出了一种实现各仲裁线之间的转换、切实可行的实际电路。

The mechanism of local bus arbitration is different from CPU and interface chip in the GPIB-VXI controller module .

在总线仲裁机构设计中应用了复杂可编程逻辑器件CPLD，固化了和总线仲裁有关的总线逻辑关系。

The complex programmable logic unit CPLD was applied in the design of the bus arbitration organization .

OPB总线仲裁器的RTL设计与FPGA实现

The RTL design and FPGA implementation of OPB arbiter device

整个DSP芯片包括测试电路和各种外围设备，如DMA、总线仲裁、定时器等等。

The implemented DSP chip includes test circuits and various peripherals , such as DMA , bus arbitration , timer , and so on .

文章介绍了在PCI系统结构中新的总线仲裁机制，提出了加权优先循环算法。

This paper presents a new PCI arbitrating scheduling scheme to support premium service in the PCI system architecture , called Weighted Priority Rotational Algorithm .

PC与DSP的数据交换采用高速静态RAM，并设计总线仲裁电路及相应的握手信号，以保证PC与DSP双方对RAM的正确读写。

PC and DSP exchange data using high speed static RAM and bus arbitration circuit and corresponding handshake signal is designed to ensure the correct reading and writing RAM .

该设计将DDR控制单元和系统内部总线仲裁单元较好地整合成统一的控制器。

DDR control unit and system local bus arbitrate unit are merged in one controller harmoniously .

本文提出了一种具有实时性、可扩性、采用总线仲裁链式结构的多微机系统CMMS。

A multi-microprocessor ( CMMS ) based on chained arbitration-bus structure is proposed with real-time ability and extensibility .

ATM侧利用轮询和优先级控制共用来实现信元总线仲裁，从而实现业务服务质量控制，并提高信元传输效率。

On ATM side , both polling and priority control are used to perform cell bus arbitration . So the QoS control is provided and the cell transfer efficiency is enhanced .

DMA的性能及总线仲裁在其他页面的“DAB，DCB和DEB性能”中可以找到。

Performance and bus arbitration for DMA can be found in " DAB , DCB , and DEBPerformance " on another page .

本文提出一种以共享RAM为信息交换界面的多微机系统，着重讨论了总线仲裁电路、总线隔离电路的工作原理和工作时序。

This Paper puts forward a multimicrocomputer system with shared RAM as message & switching interface . The operating principles and sequence of bus arbitrating circuit and bus isolating circuit are discussed .

描述了CMMS系统结构及总线仲裁链式环逻辑，介绍了通信软件设计思想，并给出了发送和接收程序流程图。

The architecture and logic of chained arbitration-bus , the design idea of communication software , and the diagrams about transmitting and receiving are given .

电路方面，文档录入机的控制电路和USB接口电路是整个系统设计的重点，而USB与文档录入机的信号采集共用数据线和地址线，因此数据和地址总线仲裁是设计的难点。

In the circuit aspect , it record into with document the semaphore of the machine collect to use the data wire totally and address wire , avoid the data and the clash of address is to design a little bit difficult .

并在高速电路设计理论指导下完成了系统硬件平台PCB设计。提出了基于总线仲裁的新型多DSP对等全互连结构，该方法结构简单，数据传输灵活，多个DSP地位平等，不分主从。

The PCB of hardware system is completed under the guidance of high-speed circuit design theory . A new multi-DSP parallel interconnected structure based on bus arbitration is presented , which has the features of simple structure , flexible data transfer and multiple DSPs in equal status .

同时，论文详细阐述了报文定时、总线仲裁、主权转移、热备份等MVB模块设计所涉及的关键技术，其中主权转移和热备份是MVB模块设计新的尝试。

Main key technology as telegram timing , mastership transfer , hot back-up were described detailedly . At the same time , a new try on the design of mastership transfer and hot back-up was promoted in the paper .

基于一款超扭曲阵列液晶显示（STN-LCD）控制驱动器的专用集成电路（ASIC）的设计与实现，从功耗管理、时钟规划和总线仲裁三个方面阐述了低功耗系统规划方法；

The design and implementation were investigated of application specific integrated circuit ( ASIC ) used in a super tortuosity nomograph liquid crystal display ( STN-LCD ) controller & driver . The low-power system specification techniques including power management , clock planning and bus mediation were expounded .

总线仲裁器模块广泛地应用于控制类芯片的各个领域。

Bus arbiter module is used in many fields of industry control .

本文介绍了一种总线仲裁器的逻辑电路。

In this article the design of a cost-effective bus arbiter is discussed .

多微处理器系统中总线仲裁逻辑的设计

The design of bus arbitrating logic on multiprocessor systems

多机多级动态优先级总线仲裁器的研究

Research of A Multilevel & Priority Dynamic Bus Arbiter

一种固定优先级分布式总线仲裁器的设计方法及性能评价

A Fixed Priority Level Distributed Bus Arbiter ' r 、 Design Method and Performance Evaluation

一款嵌入式芯片总线仲裁器的设计和评估

Design and Evaluation of SoC Bus Arbiters

分布式总线仲裁器的设计

Design of the Distributed Bus Arbiter