门阵列

门阵列CAD软件的设计

Software & Tools A Design of CAD Tools for Gate Array

我们选择FPGA（现场可编程门阵列）作为并行处理平台。

We selected FPGA ( Field Programmable Gate Array ) platform for parallel processing .

设计了一种以DSP（数字信号处理器）和FPGA（现场可编程门阵列）为核心的图像压缩系统。

An Image Compressing System is designed with DSP and FPGA .

现场可编程门阵列第四讲FPGA在雷达信号处理系统中的应用

Lesson 4 Application of FPGA in Radar Signal Processing System

用现场可编程门阵列（FPGA）实现步进电机平滑运行。

The smoothly running of step motor can be implemented using FPGA .

对于接口板，我们用可编程门阵列（FPGA）来实现其功能。

For the interface board , we use FPGA to realize its function .

提出一种采用现场可编程门阵列器件FPGA实现音频处理芯片的方案。

An audio processing chip is designed by using FPGA in this paper .

探讨现场可编程门阵列（FPGA）器件编程数据的装载模式及过程。

The loading mode and process of programmable data of FPGA device are discussed .

本文以现场可编程逻辑门阵列FPGA为核心，对定向扫描控制电路进行了设计。

By using FPGA as the controlling carrier , scan control circuit is designed .

利用现场可编程门阵列FPGA开发专用实时图像处理系统芯片

Real-time Figure Process System Chip Development With FPGA

系统采用现场可编程门阵列（FPGA）实现。

The system is implemented successfully with field programmable gate array ( FPGA ) .

该算法充分考虑了可实现性和实时性并采用现场可编程门阵列（FPGA）设计实现该算法。

With implementation fully taken into consideration , the algorithm is implemented by adopting FPGA .

所以制造商通常使用现场可编程门阵列（FPGA）。

So , instead , manufacturers often use field programmable gate arrays ( FPGAs ) .

讨论了一种基于现场可编程门阵列（FPGA）的数据加密标准算法实现。

The paper presents a DES implementation based on FPGA and proposes optimal resource scheme .

FPGA（现场可编程逻辑门阵列）用做高速数据采集系统的主控制器具有单片机、DSP等通用CPU所不具备的特点：并行执行、速度快、低功耗等。

FPGA has the characteristics of parallel executing , high speed , low consumption , etc.

现场可编程门阵列（FPGA&FieldProgrammableGateArray）是新型的大规模集成逻辑器件。

The FPGA ( Field Programmable Gate Array ) is a new large-scale integrated logic IC .

在此基础上，利用Uk门阵列实现三值时序电路。

Based on it , ternary sequential circuits are implemented by using array of universal-logic-module Uks .

现场可编程门阵列（FPGA）是数字集成电路芯片，具有可重新配置的特点。

Field programmable gate array ( FPGA ) is a digital integrated circuit chip and reconfigurable .

FELLOWCMOS双层金属工艺的门阵列版图设计系统

FELLOW CMOS Double Metal - Layer Gate Array System

采用现场可编程逻辑门阵列（FPGA）技术的设计方法

Design Method Based on FPGA

可编程逻辑，特别是现场可编程门阵列（FPGA）便是这样的解决方案。

Programmable logic , in particular field programmable gate array ( FPGA ) is such a solution .

通过利用现场可编程门阵列FPGA设计微控制器的接口电路，使得电路的设计变得简单灵活。

The design of interface circuits of micro controller becomes simple and flexible due to using FPGA .

第二部分是利用FPGA（FieldProgrammableGateArray，现场可编程门阵列）来实现HDLC协议。

The second part uses FPGA ( Field Programmable Gate Array ) to realize the HDLC protocol .

半客户式CMOS门阵列电路设计方法

The Design Method of Semi-Custom CMOS Gate Array

现场可编程门阵列（FPGA）包含有大量实现组合逻辑的资源，可以完成较大规模的组合逻辑电路设计，提高系统的集成化。

FPGA includes such great number of resources for realizing combinatorial logic to complete large-scale combinatorial circuit designing .

目前大规模可编程的逻辑门阵列FPGA为传动误差测试系统的设计提供了新的技术手段。

The design of detecting system of Transmission Error , currently , is provided new technology by FPGA .

目前大多数可重构计算技术的研究成果基本由现场可编程门阵列器件FPGA和通用处理器构成，由可编程器件提供对复杂运算的加速计算能力。

At present , the research productions of reconfigurable computing are basically composed of FPGA and general-purpose processor .

而现场可编程门阵列器件（FPGA）是一种可以进行重编程和重配置的芯片，可以方便地设计出所需的硬件逻辑。

Additionally FPGA users can conveniently not only design the hardware logic required , but re-program and re-configure .

双层金属布线2μMCMOS万门门阵列（LC4750）工艺研究

Study of 2 μ m CMOS Process for 10000 Gates Array with 2-level Matel Interconnect

基于可编程门阵列（FPGA）器件实现了低功耗的高速光互连链路。

A low power-dissipation gigabit-per-second optical interconnection data link was realized using field programmable gate array ( FPGA ) .