最大功耗

从硬件电路以及软件设计部分着重考虑到功耗问题，整个系统的最大功耗为250mW/3.3V（持续时间为一帧图像的时间）。

The power consumption is primarily put emphasis on during the design of hardware and software . As a result , the maximum power consumption for the whole system reaches as low as 250mW / 3.3V for the duration of one frame time .

用遗传算法实现CMOS时序电路最大功耗估计

Maximum Power Estimation for CMOS Sequential Circuits by Genetic Algorithm

一种新的CMOS组合电路最大功耗快速模拟方法

A Novel Approach to Fast Simulate Maximum Power Dissipation of CMOS Combinational Circuits

CMOS电路最大功耗宏模型

Macro Model for Estimating Maximum Power of CMOS Circuits

最大功耗估计问题是一个NP难题。

Maximum power estimation is a NP-hard problem .

基于ATPG的最大功耗估算改进算法

Improved ATPG-Based Maximum Power Estimation

基于GSAA算法的组合电路最大功耗估计方法

Maximum power estimation for CMOS combinational circuits based on genetic-simulated annealing algorithm

串联型稳压电路中调整管最大功耗的讨论

Discuss on Maximum Power Dissipation of Pass Transistor Serial Voltage Regulator

基于贝叶斯推理和向量压缩技术的最大功耗分析

Maximum Power Analysis Based on Bayesian Inference and Vector Compression Techniques

计算串联稳压电路调整管的最大功耗的另一种方法

Another Way to Calculate the Maximum Power Dissipation of Regulator in Serial Voltage Regulation Circuit

因此本文就对门级电路的最大功耗估计技术进行了研究。

In this paper , the maximum power estimation technique of the gate level is studied .

在异构并行处理引擎级功耗控制中，文章提出了应用感知的最大功耗管理方法。

In the heterogeneous processing engine level power manage-ment , we propose an application-aware peak power management .

这可以从不同的焊接到焊盘的大小给予最大功耗最小焊盘尺寸。

This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation .

研究表明：乱序执行将操作的功耗差别在时间轴上进行平均，可以降低最大功耗差别。

The research concluded as the following : Execution in random order averages the power significance of the operations over the time axis and thus decreases the maximal power-distinction .

CMOS电路的最大动态功耗计算和测试生成

Calculation and Test Generation of the Maximum Dynamic Power Consumption lor CMOS Circuits

最大摩擦功耗出现在压缩上止点附近。

The maximum friction power loss occurs near the top dead center of compression .

一种基于最大偏差的AES功耗分析攻击方法

Power Analysis Attacks Against AES Based on Maximal Bias Signal

此外，片上集成的模拟外设的正常工作电压降至1.8V，这有助于简化应用设计以及最大限度降低整体功耗需求。

In addition , integrated analog peripherals are fully functional at supply voltages down to1.8V.This can help simplify design as well as helping to minimize overall power demand .

结果同一核心缝合法时，Halsted法的2-mm间隙形成负荷、最大负荷、最大功耗最高；Cross-stitch法次之；

Results While the same core suture technique was used , the 2 mm gap formation force , maximum load , and maximum energy consumption were highest for the Halsted peripheral suture technique , secondly for the cross stitch suture , and lowest for running suture .

采用破碎功耗理论确定该破碎机的驱动功率，并对相应配套的的传动装置进行了设计计算，最大程度的降低功耗比。

It applied the theory of broken power consumption to determine the driving power of the crusher and designed the corresponding transmission device .

本文利用最大功率传递定理，对调整管的最大功耗进行了分析计算。

This paper analyzes and calculates the maximum power dissipation based on the theorem of the maximum power transfer .

结果表明，较低的拉应力下，微动疲劳寿命显著降低，其最大降低对应的接触应力下，微动副具有最大的摩擦功耗。

The test results show that fretting fatigue life heavily declines at low tensile stresses , and its greatest decrease corresponds to the contact pressure at which the dissipated friction work is the maximum .