下拉电阻
- 网络Pull down;Pull-down resistor;Pull-Down Resistance;pulldown;Pull-low
下拉电阻-
微处理器管脚用下拉电阻R1与地相连，阻抗典型为几百千欧，在管脚上呈现出高阻状态。
The microcontroller 's pin connects to ground using pulldown resistor R1 with resistance , typically , of a few hundred kilohms to impress the high-impedance state on the pin .
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如将其值的一半接到5V电源做上拉电阻，将另外的一半拉接到地做下拉电阻，则各个节点的两边偏置电阻最大总共为685Ω。
Placing half of this value as a pullup to5V and half as a pulldown to ground gives a maximum bias resistor value of685 Ω for each of the two biasing resistors .
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文章介绍了一种用在高精度A／D转换器中的CMOS电压参考源，依靠PMOS管阈值电压差来产生电流，在外接下拉电阻上产生电压参考源。
In this paper , it introduces one kind of CMOS voltage reference source in high precision A / D converter , which produces current depending on difference of PMOS threshold voltage , and gives birth to voltage reference source on external get-down resistance .