逻辑摆幅
- 网络logic swing
逻辑摆幅-
通过采用恒定工作电流和限制电路的输出逻辑摆幅，电流控制逻辑能避免静态CMOS电路工作时引入的瞬态开关噪声电流。
Using a constant biasing current and a reduced output logic swing , current-steering logic avoids the large digital switching noise of conventional static CMOS logic .
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本文介绍一个÷5/6低功耗ECL予置分频器的设计，从降低电源电压，减小内部逻辑摆幅和寄生电容等几方面讨论了提高电路高速低功耗特性的途径。
The design of a ÷ 5 / 6 low power ECL prescaler is described in the paper . Approaches to improve the high speed and low power property of the circuit are discussed in terms of the reduction of supply voltage , internal logic swing and parasitic capacitance .