减法器

算法由n位并行减法器、n位数据搜索器和其他4个子算法组成。

The proposed algorithm consists of an n-bit parallel subtracter , an n-bit parallel searcher , and other four sub-procedures .

设计了具体的LED光源的驱动电路，以及前置放大器、减法器等的具体电路。

Have designed the concrete drive circuit of LED light sources and the concrete circuits of preamplifier and subtracter , etc.

该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。

Program of the N-bit-wide reduction , the first realization of a subtraction for , after all N-reduction devices .

FPGA上浮点加/减法器的设计

Design of Floating Adder on FPGA

事实上，对于映射器和为整数求和而预定义的减法器，我们可以使用size（）方法的方法引用，更紧凑地表达此过程

In reality , we would probably express this more compactly using a method reference to the size () method for our mapper and a predefined reducer for integer summation

采用Veriloghdl语言描述了系统的逻辑功能，超前进位结构的加/减法器提高了电路的工作速度。

Using Verilog HDL describes the logic function of the system . The carry lookahead adder or subtracter raises the working speed of the circuits .

这里，第一个lambda表达式是映射器（将每个元素映射到它的大小），第二个lambda表达式是一个减法器，它获取两个大小并相加。

Here , the first lambda expression is the mapper ( mapping each element to its size ), and the second lambda expression is the reducer , which takes two sizes and adds them .

这种分子减法器电路的实现对分子电子学发展有重要的意义。

This work is a significant milestone in molecular electronics .

高阻抗高共模抑制减法器研究

Study on High Impedance Subtractor with High CMR

减法器（16）从读取信号中减去所述串扰信号。

A subtractor ( 16 ) subtracts the crosstalk signal from a read signal .

基于聚亚苯基分子器件的二进制减法器

Binary Subtractor Based on Polyphenylene Molecular Device

基本运算单元包括18位自定义的的浮点数加法器、减法器、乘法器和除法器。

Computing units includes a custom 18-bit floating-point adder , subtraction , multiplier and divider .

取补线路可任意选通减法器的输出或补取线路的输出。

A complementing circuit selects either the subtracter output or the output of the complementing circuit .

加法器与减法器产生测试向量的原理与累加器的相同。

The principle of the adders and subtractors to generate test vectors is the same as that of accumulators .

本文介绍了采用脉冲同步方法的两种脉冲减法器的方案及设计思路。

Two kinds of schemes and their designing consideration of pulse subtracter by using the method of pulse synchronization are described in this paper .

详细讨论了32位浮点加法器/减法器、乘法器的分级流水技术，提高了系统性能。

The pipelining technique of 32 bit floating-point adder / subtracter and multiplier is introduced in detail , which can enhance the performance of the FFT processor .

把所述自适应滤波器（15）和减法器（16）与异步时钟（18）耦合以便以异步采样率操作。

The adaptive filter ( 15 ) and subtractor ( 16 ) are coupled to an asynchronous clock ( 18 ) for operating at an asynchronous sample rate .

为了在分子电路水平实现减法运算，按照固态电子学组合逻辑原理，提出了一种基于聚亚苯基分子器件的二进制减法器（包括半减器和全减器）逻辑电路的设计。

In order to implement subtraction circuit in molecular scale , based on the principle of solid-state electronic circuit design , a binary subtractor based on polyphenylene was proposed .