测试生成

数字IC可测性设计和自动测试生成技术

Design for Testability and Automatic Test Generation Techniques for Digital IC ′ s

然而，理论分析证明，自动测试生成的时间复杂性是个NP完全问题。随着电路规模的增大，测试生成越来越困难。

But theoretical analyze proofs that time complexity for automatic test generation is an NP-completeness problem .

第一个测试生成一个true结果，所以表达式求值会继续下去。

The first test produced a true result , so the expression evaluation continues .

测试生成的JavaAPI参考文档。

Test the Java API reference documentation that was generated .

SAT数据结构与组合测试生成

Efficient Data Structure for SAT Solvers & Combinational Test Generation

当测试生成过程完成之后，测试集将在TestEditor视图中打开。

After the test generation process is complete , the test suite will open in the Test Editor view .

通用数字IC的测试生成研究

On the test generation of general-purpose digital ICs

测试生成所需的计算量的上限是2（n1+4n2）~2。

The upper bound of the magnitude of computation for test generation is 2 ( n1 + 4n2 ) 2 .

CMOS电路开关级测试生成

Test Generation at Switch Level for CMOS Circuits

本文讨论CMOS静态组合电路开关级上的测试生成方法。

This paper discusses the test generation of CMOS static combinational circuits at switch level .

含ROM和RAM芯片的数字电路板测试生成

Test Pattern Auto-generating for Digital PCB with RAM and ROM

VLSI的动态功耗测试生成

Test Generation of the Dynamic Power Consumption for VLSI

二元判定图（BinaryDecisionDiagram，BDD）的有效描述将大大提高验证和测试生成效率。

Effective description for Binary Decision Diagram ( BDD ) has proven useful in many applications as data structure for Boolean function .

根据本算法，用FORTRAN语言编制的一个测试生成程序，已在PDP-11/23机上实现。

On the basis of the algorithm a program written in FORTRAN ⅳ has been developed on PDP-11 / 23 .

ASIC测试生成和可测性分析系统ATGTA

Atgta : an ASIC test generation and testability analysis system

在SVM测试生成算法中，每个电路状态，包括正常或故障状态都需要一个单独的测试信号。

In the test generation algorithm based on SVM , every circuit instance , which may be normal or faulty instance of the analog system , needs a unique test signal .

基于加法器测试生成，提出了无限脉冲响应（IIR）滤波器的一种通用可测性设计、测试方案。

Based on arithmetic additive generator , we present an universal design-for-testability and test strategy for infinite impulse response ( IIR ) filter .

详细论述了故障分解的理论和两种故障分解算法的基本模型，并且在实现了一个基于FAN算法的并行测试生成系统的基础上详细说明了故障分解的并行测试生成算法的具体实现。

The theory of fault allocation and two basic models of fault allocation are discussed in detail in the paper . Then a concrete implementing is explained carefully after realizing the parallel test based on the FAN Algorithm .

阐述了一种基于混沌神经网络的自动测试生成（ATPG）算法。

A new automatic test pattern generation ( ATPG ) methodology based on chaotic neural network method is described .

INAP协议一致性测试生成的形式化方法

INAP Protocol Conformance Testing Using Formal Method

因此，将Petri网的分析方法与计算机仿真的数字电路相结合，提出了基于Petri网的仿真电路模型、故障模型以及相关的测试生成、测试集化简方法。

Therefore , we combine Petri net analysis method with software simulated circuit , put forward Petri net based simulated circuit model , Petri net based fault model and related test set generation method , test set simplification method .

组合电路测试生成的PODEM算法及实现

Podem Algorithm and its Realization on Combined Logic Circuits

IHDL语言与测试生成系统

Ihdl and an automatic test generation system

一个有效的通路时滞故障测试生成系统DTPG

Dtpg : an efficient test generation system for path delay faults

研究了基于二值Hopfield神经网络的组合电路测试生成算法。

The test generation algorithm based on Hopfield neural networks for combinational circuits is studied , three-valued neural networks is applied in the test generation and the test generation algorithm based on three-valued neural networks for combinational circuits is proposed in the paper .

本文详细地介绍了一种集成式硬件描述语言（IHDL）和与IHDL相适配的门级电路测试生成系统，实现了从硬件描述语言编译器到自动测试生成的完整系统。

Two-Dimensional Numerical Scheme for SOI CMOS Gate An Integrated Hardware Description Language ( IHDL ) and an automatic test generation system based on IHDL are introduced in this paper .

基于搜索状态控制的组合电路测试生成算法

Test Generation Algorithm Based on Search State Dominance for Combinational Circuits

组合电路桥接故障诊断的测试生成及优化

Test generation and optimization of bridging faults diagnosis in combinational circuit

在数字电路最优神经网络模型的基础上，研究基于该模型的电路测试生成方法。

An optimal neural network model for digital circuits is studied .

第一次测试生成的数据，如下所示

From the first test run , the values generated were