扫描链

基于双核扫描链平衡的SoC测试调度

SoC Test Scheduling Based on Scan Chain Balance of Pair Cores

Wrapper扫描链均衡与系统芯片测试调度的联合优化算法

Wrapper Scan Chain Balance and Test Scheduling Co-optimization for Core-Based System-on-chip Test

约束输入精简的多扫描链BIST方案

Constraint Input Reduction BIST Scheme for Multiple Scan Chains

协议层由JTAG信号仿真、状态转换机和边界扫描链三个模块组成。

The protocol layer consists of JTAG signal stimulation , state machine and boundary-scan chain modules .

基于IP设计技术，给本电路增加了扫描链，可以作为一个IP软核应用于集成电路的可测试性设计。

Based on IP design technique a scan chain is inserted in the design . The code of this paper can be used as a IP soft core in the process of IC testable design .

实现了对内核测试壳单元的功能数据路径测试，并改善了内核测试壳单元扫描链安全移位，同时实现了允许共用同一条测试总线的不同IP核直接连接到测试总线上。

This architecture can test the data path of wrapper cells and resolve the problem of safe shifting of scan chains during shifting , also allows different cores to be connected directly to the same test bus .

通过采用调试接口电路的流水线映像寄存器组和特殊数据通路，可以避免在CPU关键路径上插入扫描链实现“非侵入性”的调试功能。

By using pipeline shadow registers and special data path in debug interface circuit , scan chain is no longer needed to insert in the critical path of CPU to facilitate non-intrusive debug capability .

实验中分析了IC故障类型、一般故障诊断流程和进行扫描链本身完整性测试的方案，并提出了一种外加测试码向量生成的算法。

In the experiments , the fault type of IC test bus , the fault diagnosis flow and the test principles were analyzed , and a fault diagno - sis strategy of test bus was proposed .

仿真结果显示，插入扫描链后电路的面积和功耗有少量增加。最后本文对NoC测试技术的未来发展方向进行了展望。

The result shows that the area and power of the circuit exhibits a little increase . Finally , the paper looks forward to the NoC test technology .

在边界扫描链设计中，采用了自定义的控制、数据、地址寄存器与指令寄存器相结合的访问ROM和RAM等相应空间方法，与原有的地址译码电路相结合，减少了硬件的开销；

The boundary scan adopts the address , data , control register together with instruction register to access relevant space , utilizes original circuit of core of DSP , decreases the cost of hardware ;

其次，通过对基于总线的扫描链的移位操作插入目标系统CPU本身的指令，并在硬件调试模式下单步执行这些指令，对系统内部的总线数据、寄存器数据、存储器数据进行修改。

Secondly , through the bus-based scan chain shifting CPU instructions into the target system , and implementation of these instructions by single step in hardware debug mode , to modify the bus data , register data and memory data .

本方法可以直接用扫描链作为CSR（CirculatingShiftRegister），从而节省了硬件开销，并且本文的方法解压结构简单。

The decompression hardware implement is not complex and it directly use scan as CSR for saving hardware . Using AFS algebra and AFS structure , any human ordinary fuzzy concept can be represented .

基于Multi-Capture结构的扫描链优化算法

Scan Chain Optimization Algorithm in Multi-Capture Structure

首先在驱动层的基础上实现JTAG操作接口，该接口向调用者提供读写数据、指令寄存器，读取控制器标识，设置扫描链及重启等功能函数。

Based on the driver of JTAG , a set of functions is provided including data / instruction register reading / writing , chain selecting , bypassing and resetting to the caller .

为了压缩测试向量并降低芯片测试成本，本文提出了一种新的基于最小相关度扫描链的多捕获（Multi-capture）测试结构。

A Multi-capture scan testing based on Minimum Relativity chain structure is proposed in this paper to compact the larger and larger test patterns .

我们用TILE中的可编程资源构建扫描链，并根据GRM中的开关方向，将测试分为水平向测试，垂直向测试，左倾测试及右倾测试。

We use the programmable logic resource in TILE to build scan chain . Based on the direction of switch in GRM , we classify the testing into horizontal testing , vertical testing , left diagonal testing and right diagonal testing .

根据网络表文件和BSDL文件生成测试图形，通过PC机的并行口传送测试协议信号，利用该系统进行了PCB板级的扫描链完整性测试和芯片的互连测试。

According to the network table file and the BSDL file generation test pattern , through the parallel port PC-test protocols to send signals , using the system for a PCB board-level scan chain makes integrity test and chip interconnect testing .

在JTAG接口协议的基础上，增加指令和扫描链，同时通过测试访问端（TAP）控制把串行输入转换成并行输出，并行访问数字信号处理器的寄存器文件和片上存储器单元，实现嵌入式模拟器。

Based on the jointed test action group ( JTAG ) protocol , instructions and scan chain were introduced . With test access port ( TAP ) module exchanging serial input with parallel output , register files and random access memory on chip were read or written in parallel .

可变长度边界扫描链的设计与仿真

The Design and Simulation of the Length configurable Boundary Scan Circuit

基于多扫描链的测试数据压缩方法研究

The Research of Test Data Compression Based on Multiple Scan Chains

因此，阻塞部分扫描链时钟的技术被提出来以降低测试功耗。

Scan chain disable technique has proposed to reduce test power .

基于多扫描链相容压缩的距离标记压缩方法

Distance-marking compression method based on compatible compression of multiple scan chains

减少数字集成电路测试时间的扫描链配置

On Scan Chains Configuration for Reducing Test Time of Digital Integrated Circuits

多扫描链测试集的分组标准向量压缩法

Standard Vector Compression Based on Test Set Grouping in Multiple Scan Chains

基于多扫描链的内建自测试技术中的测试向量生成

Test Pattern Generation in Built-In Self-Test with Multiple Scan Chains

通过单扫描链的构造实现最小测试应用时间

Constructing single scan chain for minimum test application time

基于组合解压缩电路的多扫描链测试方法

A Multiple-Scan-Chain Test Approach Based on Combinational Decompression Circuits

一种基于概率分析的扫描链动态功耗模型

A Probabilistic Study of Scan-based Testing Power Consumption

而在传统测试方法中，整条扫描链都工作于测试模式。

However , all scan chains work at the same time in traditional method .

在利用较少的测试端口的情况下，最长测试壳扫描链长度得到普遍缩短；

The length of scan chain is shortened under limited test ports at large .