测试向量

基于I（DDT）的BIST测试向量生成器的研究

The Research of BIST Test Vector Generation for I_ ( DDT ) Testing

在故障诊断能力和测试向量长度不变的前提下，得到了针对WA的算法。

Under the conditions of fault diagnosing capability and test vector length are not changed , an algorithm for W-A is acquired .

检测CMOS电路中的开路故障通常需要使用测试向量对。

To test the open-circuit failures in CMOS circuits usually needs to use test vector pairs .

一般来说平均每个SoC芯片上就拥有数百亿位的测试向量。

In general average SoC chip has tens of billions of bit of test vectors .

基于FPGA的数字视频接口（DVI）测试向量发生器

Test - vector Generator for Digital Visual Interface Based on FPGA

基于部分测试向量切分的LFSR重新播种方法

LFSR Reseeding Based on Syncopation of Some Test Patterns

VLSI测试向量自动生成工具（TGtool）的研制

VLSI Test - vector Generation Tool ( TGtool ) Research

对于这些测试向量对，通过SPICE软件模拟了故障电路和无故障电路在测试向量对作用下的动态电流。

SPICE experiments were done to simulate the dynamic currents of both the fault circuits and fault free circuits under the function of testing pairs .

本文主要介绍了VLSI测试向量自动生成工具（TGtool）的原理、结构和实现方法。

This paper introduces the principle of VLSI test-vector automatic and how to generate VLSI test-vector .

分析测试向量转换过程，研究ATE测试向量转换技术，重点研究VCD电平分离、测试时序提取、测试向量生成和测试向量压缩等关键技术。

We analyze the process of test vector conversion , research the key techniques of VCD level separation , test timing extraction , test vector generation and test vector compression .

介绍了VLSI功能测试向量生成的Petri网模型和Petri网模拟测试序列中指令的关系，构造了压缩存储网络的拓扑信息的Petri网简约矩阵。

This paper introduces Petri net model of functional test pattern generation for VLSI . Relationships between operators involved in test sequence are accomplished via Petri . Reduced matrix compacting storage of net topology is constructed .

文章提出了一种基于自动测试向量生成（ATPG）的ASIC前端验证环境的构建方案，方案整合C，TCL和Ver鄄ilogHDL语言，有着良好的实用性和可扩展性。

This paper brings forward a building scheme of atpg-based ASIC verification environment . It has integrated C , TCL and Verilog HDL languages to achieve good practicability and expansibility .

实验结果表明，在相同的转换条件下，当测试向量较大时，SpeedyE2A（S）系统的转换时间远远少于Credence的TDS系统。

Experimental results show that SpeedyE2A ( S ) can significantly reduce the translation time compared with TDS when translating large test vectors .

一种基于TRC-LFSR结构的二维测试向量压缩设计

Design of the 2-dimensional test patten compression based on TRC-LFSR structure

密钥长度及加密/解密模式由用户控制，程序主要用于产生测试向量进行后期IC设计测试，也可应用于文件的加解密操作。

Both the key length and the encryption / decryption operation mode can be controlled by users . This program can be used not only to generate testing vec ˉ tors for IC design and test , but also to encrypt / decrypt general documents .

本文针对由被测电路自己产生测试向量取代LFSR伪随机向量，提出一种基于遗传算法的自动测试向量生成算法。

For substituting the test vectors generated by the circuit under test for the pseudo-random vectors supplied by a LFSR , this paper proposes an ATPG algorithm based on genetic algorithm .

本文对ABEL开发软件的GAL器件库定义、逻辑功能描述方法、测试向量的确定以及源文件的处理等关键应用技术问题进行了深入探讨。

This paper investigated deeply the key problems of application techniques of ABEL software , such as the definition of base of GAL devices , the logic functional descriptive method , the defining test vector and source files processing , etc.

为了压缩测试向量并降低芯片测试成本，本文提出了一种新的基于最小相关度扫描链的多捕获（Multi-capture）测试结构。

A Multi-capture scan testing based on Minimum Relativity chain structure is proposed in this paper to compact the larger and larger test patterns .

该方案基于RTD电路开关级模型，针对电路基本的开路、短路故障合理增加控制端，利用控制端信号设计测试向量，使电路达到完全可测的目的。

Combining the switch-level model of RTD circuits and the basic principle of open faults and short faults , the control signals were added to generate the test benches by utilizing the control signals reasonably to achieve the full testability .

同时还提出了基于ASIC的人脸检测硬件架构。（4）在视频监控所用的芯片中，集成视频分析引擎的芯片往往规模很大，会生成大量的测试向量。

Hardware architecture for face detection based on ASIC has been presented in the end . ( 4 ) The chips used in video surveillance which include video content analysis are usually large in scale , which will generate a great number of test vectors .

结果表明，该方法的验证速度可以达到200KHz，在针对相同的DUT的情况下，该方法的验证速度比软硬件协同验证的联合验证模式和测试向量模式的速度高出2倍以上。

The result shows that the verification speed is 200 KHz . The verification speed is 2 times faster than that of the other two verification mode for the same DUT .

同时，本文使用verilog-XL编写测试向量，对加法器进行完全仿真测试，确保了逻辑功能的正确性。

At the same time , we simulate the adder with test vectors of verilog-XL . The full simulation can make sure of the correctness of the logical function .

经SpeedyE2A（S）系统转换的8051和海尔爱国者芯片的测试向量，已经成功地在北京自动测试技术研究所的测试系统上运行。

The translated vectors by SpeedyE2A ( S ) are successfully applied to test 8051 microcontroller and Haier HDTV integrated circuits on the ATE of Beijing Automated Test Technology Institute .

基于解压缩实现难易程度的折衷考虑，提出了基于Golomb算法的便携式检测设备的测试向量压缩方法，采用VHDL方法设计了相应的硬件解压缩电路，并且将其应用于便携式飞参检测设备。

Based on the trade-off of the data decompression difficulty , a method of test data compression using the Golomb algorithm is provided for the portable test equipment . Then the corresponding decompression circuit is designed with the VHDL ( very high speed integrated circuit hardware description language ) .

本方法的解压缩电路简单、硬件开销小、测试向量的压缩率高。

The decompression circuit is simple and hardware overhead is small .

一种数字电路的测试向量生成算法

A Test Vectors Generation Algorithm for Digital Circuits Component Fault Diagnosis

微控制器测试向量生成方法的研究和实现

Research and Realization on the Generating Method of Test Vectors of Micro-Controler

故障模拟中的测试向量选择

Choice On the Selection of Test Pattern in Fault Simulation

覆盖状态内部分枝的测试向量生成

State Coverage Enhancement Considering Inside Branches and Test Pattern Generation

基于测试向量压缩的多核并行测试

Concurrent Testing of Multiple Cores Based on Test Vectors Compression