摆幅

在驱动50Ω输出负载的条件下，1.25Gbit/s的高速输出数据信号摆幅可达到410mV。

Driving a 50 Ω load , the serial output data signal at 1.25 Gbit / s has an amplitude of 410 mV .

弧焊机器人摆动跟踪时摆幅与频率的模糊模式识别

Fuzzy pattern recognition of weaving amplitude and frequency in seam tracking of arc welding robot

一种高共模输入范围高输出电压摆幅的CMOS运算放大器

A high common-mode input range and high output swing CMOS operational amplifier

低电压全摆幅恒跨导CMOS运算放大器的设计

Design of A Low-Voltage 、 Rail-to-Rail and Constant Trans-Conductance CMOS Operational Amplifier

一种低电压全摆幅CMOS运算放大器

A Low-Voltage Rail-to-Rail CMOS Operational Amplifier

输出级采用了AB类推挽输出以获得高的输出摆幅。

Output stage is a class AB to obtain the output high swing .

介绍了一种利用MOS管线性区特性实现满摆幅输入的跨导器。

A rail-to-rail input range transconductor implemented by MOS transistors linear region characters is presented .

例如，信噪比（NR）于信号摆幅的减少而降低。

For example , signal-to-noise ( SNR ) performance degrades as a result of reduced signal swing .

一种高速低耗全摆幅BiCMOS集成施密特触发器

A High-speed , Low-consumption & Full-swing BiCMOS IC Schmitt Trigger

通过采用恒定工作电流和限制电路的输出逻辑摆幅，电流控制逻辑能避免静态CMOS电路工作时引入的瞬态开关噪声电流。

Using a constant biasing current and a reduced output logic swing , current-steering logic avoids the large digital switching noise of conventional static CMOS logic .

输出级采用推挽式AB类结构，能有效地提高输出电压的摆幅，从而得到电路在低电源电压下的高驱动能力。

The output swing can be improved efficiently with push-pull class-AB output stage , thus high-drive capability with low power supply is obtained .

提出了一种工作于3V电压、输入输出均为全摆幅的两级CMOS运算放大器。

A 3-V two-stage CMOS operational amplifier with rail-to-rail input and output ranges is presented in the paper .

1.5V高速全摆幅BiCMOS逻辑电路的研究

A Study on a 1.5 V High-Speed and Full-Swing BiCMOS Logic Circuit

提出了一种多输入电压模CMOS求小/求大电路结构，它具有内部节点电压摆幅小，高速高精度以及结构简单等优点。

A new multiple-input voltage-mode CMOS min / max circuit structure is proposed , which has small voltage swing at the internal nodes , high speed , high precision , and simple architecture .

在传统两级运放的基础上，采用交叉耦合的AB类输出级和共源共栅补偿，提高了输出摆幅和带宽，并通过数学工具对功耗进行了优化。

Based on traditional two-stage amplifier , cross-coupled class AB output stage and cascode compensation were adopted to improve output voltage swing and bandwidth . Power dissipation was optimized with mathematic tools .

在输出级3V直流偏置时最大输出电压摆幅可达25Vpp。

The maximum modulation voltage is over 2.5V pp corresponding to a 3V DC bias for output stage .

LVDS正是一种采用差分信号串行传输的接口电路，其具有低电压、小摆幅的优点，被广泛应用于许多数据传输电路中。

LVDS is the serial high-speed interface based on low-voltage and low-swing differential transmission technique . It is widely used in many data transmission circuits .

AD623是一款集成式单电源仪表放大器，采用3V至12V电源供电时提供轨到轨输出摆幅。

The AD623 is an integrated single-supply instrumentation amplifier that delivers rail-to-rail output swing on a3 V to12 V supply .

结果表明，在3.3V电源电压下，电压输出摆幅为2.7V。

The result shows that the output swing is 2.7 ? V with 3.3 ? V single supply .

本文主要研究高速分频电路及其应用。完成了一种电流模式逻辑（CML）分频器设计，电压输出近似为满摆幅，可以直接和CMOS逻辑电路相连而不需要电平移位电路。

This work mainly focused on research of high speed frequency divider and its application . A current mode logic divider with nearly full voltage swing was designed . The divider could be directly connected to CMOS logic without level shifter circuit .

特别地，为了减少PLL的锁定时间，在偏置电路中引入限频电路；为了给PLL提供全摆幅的是信号，在VCO的输出电路后设计了整形电路。

In order to reduce the lock time of PLL , the frequency limiting circuit is introduced to this VCO . In order to provide a full swing of frequency source , a shaping circuit is introduced in this VCO .

该偏置电路原理是利用一个始终工作在线性区的MOS管来使共源共栅电流镜的两个级联管均工作在饱和区边缘提高输出电压摆幅，从而降低电源电压。

The bias circuit using a MOS transistor which always operate in linear region to bias the two transistors of the cascode stage operating at the edge of saturation to improve the output voltage swing and subsequently low down the supply voltage .

其积分非线性误差为045个最低有效位（LSB），微分非线性误差为02LSB，满摆幅输出的建立时间小于1μs。

The integral non-linearity error is less than 0 45 LSB , and the differential non-linearity error is less than 0 2 LSB . The settling time to full swing is less than 1 μ s.

为了扩大信号的动态范围，低电压运放通常需要输入输出的信号范围能达到全摆幅（rail-to-rail）。

In order to expand the signal dynamic range , the low voltage operational amplifier usually needs the input signal scope and the output signal scope to be able to achieve rail-to-rail .

根据RSDS接口规范，围绕接口接收器最小建立保持时间的性能，重点研究低摆幅差分信号放大器的设计。

According to RSDS specification and focusing on performance of the minimum setup and hold time , the design of differential signal amplifier for RSDS receiver is analyzed in detail .

同步块使两个COM系统在高频相位确保精确的双边三电平调制技术，而微分结构确保两个COM系统处于180°的低频相位，在扬声器负载上获得最大的电压摆幅。

The synchronization block ensures precise double-sided 3-level modulation , by keeping the 2 COM systems in phase high frequency , while the differential structure ensures that the 2 COM systems are 180 ° out of phase low frequency , maximizing the voltage swing across the speaker load .

XNOR门是构成Reed-Muller逻辑的基本门电路，现有的XNOR门电路由于信号摆幅的不完全性而导致后级亚阈功耗的存在。

XNOR gate is the basic unit of Reed-Muller logic . The non-full swing signal in the existing XNOR gates causes the sub-threshold power dissipation .

由于灵敏放大器具有检测小摆幅信号并将其快速放大为全摆幅逻辑信号的功能，因此其被广泛运用于多种不同的数字电路中，例如SRAM、DRAM，I/O、A/D转化器、数据接收器等。

Sense amplifiers ( SAs ) have been widely used in many different kinds of digital circuits such as SRAM , DRAM , I / O for the functions of detecting and amplifying a small input differential signal to a full swing signal .

基于此结构，实现了一种超低压运算放大器。仿真分析表明，该运算放大器能够实现轨到轨（rail-to-rail）的共模输入电压范围和输出电压摆幅，以及较高的共模抑制比。

Based on the structure , an ultra-low voltage operational amplifier is designed , which provides a rail-to-rail common-mode input voltage range and output voltage swing , as well as a high common mode rejection ratio ( CMRR ) .

综合考虑工作速度、输出摆幅和功耗等性能之间的相互影响，改进了以CML触发器为基础的分频器；以实现高速低功耗为目标，优化了TSPC结构的分频器。

Considering the tradeoff among working speed , output swing and power dissipation , an improved divider based on CML trigger is designed . Divider based on TSPC trigger is optimized for high speed and low power dissipation .