总线周期

支持外部等待时钟信号延长总线周期。

Supports external wait signal to expend the buS cycle .

从设备FPGA内部模块主要包括本地总线周期，VME总线周期，中断请求器模块，以及定时器模块等。

The internal modules of slave FPGA equipment mainly include : the VME bus cycle , the interrupt request module , timer module and so on .

为了达到在保证车载控制网络中过程数据可靠调度的前提下尽量提高消息数据通信性能的目的，提出了MVB总线周期扫描表的优化设计方法。

To maximize the message transmitting performance on the premise of reliability of process data scheduling , an optimization method of the MVB period polling table is presented .

多功能车辆总线周期扫描表的最优化设计

The Optimization Method of the MVB Period Polling Table

该系统能发挥两种微机的优势，利用总线周期窃用和分散型共享存储器技术，实现紧耦合方式的高速通信。

The system takes advantage of both , computers and can realize high rate communication in tight coupling style , by using bus period stealing and distributional memory sharing .

子节点总线周期设计为分时机制，每个子节点在自己的总线周期内将处理后的数据发送给主节点。

Time sharing mechanism is designed for the bus period of the slave nodes , with this mechanism ; every slave node is settled to transmit processed data to the master node .

令牌目的循环时间T（TR）对现场总线PROFIBUS测控周期的影响

Impact of Token - target - rotation Time on Message Transaction Cycle Time in PROFIBUS System

用状态机和电路图的方式实现了VME总线A16/D16单周期数据读写和块传输功能；

To satisfy the need of A16 / D16 single-cycle and block data transfer capability , the method of the state machine and diagram are adopted .

为了提高主存数据总线的有效周期利用率，提出了一种面向流应用的存储调度机制。

To enhance the available cycle utilization efficiency of memory data bus , we propose a stream application oriented memory scheduling mechanism .

设计了基于内部总线的同步周期触发，定义了一致的传感器、执行器单元执行时序，以及精确光纤链路数据传输模型，确保测控的高同步性。

Design of synchronous cycle trig based on internal bus , consensus definition of sensor sampling and actuator timing and precise data transmission model ensured the synchronization performance .