并行加法器

由于加法器是ALU单元的核心功能部件，它的性能决定着整个ALU单元的性能，所以本文主要对子字并行加法器进行了设计。

The adder is the core of the ALU , and its performance greatly influence to the performance of the entire ALU , so we laid a strong emphasis on the design of sub-word parallel adder .

4个加数的并行加法器及扩展接口的研究

Research on a parallel adder with 4 binary addends and its interface

通常使用的并行加法器算法是超前进位加法算法。

Commonly used algorithm of parallel adders is Carry Look-ahead Adder ( CLA ) algorithm .

并行加法器是一种数位电路，其可进行数字的加法计算。

Consequently , several adder architectures have been proposed to meet different design requirements in the past .

在这两种机制的指导下，实现了多种子字并行加法器，并对它们的性能进行了比较和分析。

Under the guidance of those two mechanisms , this paper implements several different subword-parallel adders and analyzes their performances .

首先介绍了常用并行加法器的设计方法，并在此基础上采用带进位强度的跳跃进位算法，通过逻辑综合和布局布线设计出了一个加法器。

This paper introduces the design method of parallel adder . On the basis we design an adder by the adoption of carry skip algorithm with carry strength signals and implement , through logic synthesis and layout .

并行前缀加法器的研究与实现

Research and Implementation of Parallel Prefix Adder

时延故障对高速运算电路性能有着关键性的影响，本文对其中之一的并行前置树型加法器的通路时延故障测试作了研究。

Based on cell fault model , the paper studies test pattern generation and self test of tree adder , which is frequently used in the high performance processors .

这种新型加法器是一种以半加器为基本结构单元的异步加法器，采用了并行反馈进位方式，称为并行反馈进位加法器（ParallelFeedbackCarryAdder，PFCA）。

The new adder is an asynchronous adder whose basic unit is half adder , called Parallel Feedback Carry Adder ( PFCA ) as its carry mode is parallel feedback .