除法器

用FPGA实现先行进位单元阵列除法器

The Realization of Precedent Cellular Arrays Divider by Means of FPGA

介绍了用FPGA实现先行进位单元阵列除法器的原理及方法。

The theory and method of precedent cellular arrays divider by means of FPGA are introduced .

常数除法器的设计及其BIST实现

Design of Constant Divider and Its BIST Implement

SRT除法器及其算法的研究

Study on SRT divider and its algorithm

本文给出了以电流反馈运算放大器构成的新型模拟除法器，并用PSPICE进行了仿真分析。

New analogue divider circuits using current feedback operation amplifiers ( CFOA ) are presented . simulated analysis is given by PSPICE .

介绍了MAX+PLUSⅡ中LPM库车RAM、除法器和DDS频率合成器上进行数字系统设计的应用。

Applications of digital system design about LPM database 、 divider and DDS frequency synthesizer in the MAX + PLUS ⅱ are introduced .

该乘法器具有完整的控制接口，考虑了一个通用高性能CPU对乘法器的要求。除法器使用non-resorting算法，以无符号数除法为基础，把有符号数除法转化为无符号数除法来处理。

The divider unit uses non-resorting algorithm to deal with unsigned division and transforms the signed division to unsigned one .

本文提出了一种新型的模拟除法器&积分比较式模拟除法器。给出了由电流反馈运算放大器构成的新型模拟除法器，并用PSPICE进行了仿真分析。

An analogue divider of integral comparing mode is described . New analogue divider circuits using current feedback operation amplifiers ( CFOA ) are presented . Simulated analysis is given by PSPICE .

详细介绍了在设计RS（256252）译码器过程中所用的乘法器和除法器，两种器件具有规则的结构，有利于用VLSI硬件电路来实现。

This paper describes in detail how to design the multiplier and divider during the course of implementing RS ( 256,252 ) decoder . These two components have regular structure and can be easily realized on VLSI chips .

与MIPS微处理器中的除法器相比，它的平均执行周期减少了525%，而其最大延时几乎不变，仅晶体管数目增加了60%。

Compared with the divider of MIPS microprocessor , it decreases the average executing cycles by 52.5 % while its maximum delay is almost the same and its transistor count increases by 60 % .

其次，对电路各部分进行详细设计，即用Veriloghdl语言设计算法电路，其中包括加法器、乘法器和除法器等通用模块的设计。

Second , every units of the circuit are designed in Verilog HDL language , including the universal module such as adder , multiplier and divider , etc. Finally , the circuits are designed in top level , including the use of pipeline structure in decoder .

在除法器的设计中采用了移位相减的方法；

Magnetic Shift Adopted booth arithmetic to design multiplication module .

GB/T6812-1986半导体集成非线性电路系列和品种模拟乘-除法器的品种

Families and variety of semiconductor integrated non-linear circuits variety of analog multipliers-dividers

一种高阶除法器的设计与实现

Design and Implementation of A Very-High Radix Floating-Point Division Unit

一种新型模拟除法器及其应用

A New Type of Analogue Divider and Its Application

积分比较式除法器在压敏电阻压比测量中的应用

Measuring voltage ratio of varistor by integral comparison divider

介绍了一种采用双积分原理的数显模拟除法器。

An analogue divider with digitized output based on dual-slope integration is presented .

高性能单精度除法器的实现

Implementation of High Performance Single - Precision Divider

基本运算单元包括18位自定义的的浮点数加法器、减法器、乘法器和除法器。

Computing units includes a custom 18-bit floating-point adder , subtraction , multiplier and divider .

一种基于循环减法原理除法器的加速方法

An Accelerated Method of Circular Subtraction Division

设计完成了一种基于有限域的椭圆曲线加密算法，主要包括适合于168bit椭圆曲线加密的有限域乘法、加法、除法器的实现；

Then we show an algorithm design of the elliptic curve crypto based on Galois field .

微程序除法器的设计

A design of the microprogram divider

在分析除法器设计的泰勒级数展开算法基础上，提出了一种新的除法器设计算法。

Based on the analysis of Taylor-series expansion methods , we proposed a new divider algorithm .

子模块包括浮点加法器、浮点乘法器、浮点除法器和三角函数器。

Sub-modules including the floating-point adder , floating-point multiplier , floating-point divider , trigonometric function device .

同时利用除法器减少了光强的变化及光纤连接损耗对传感器信号的影响。

In addition , the sensor eliminates the influence of light source intensity fluctuation and the coupling and connecting loss in the fibers .

逻辑电路中主要研究了除法器、直方图统计、图像采集和中值滤波器的实现与优化。

We mainly studied the realization and optimization of the divider , histogram statistics , image acquisition and median filter in logic circuits .

为提高除法计算的速度，提出了新的基-16算法的高速除法器算法，并以专用集成电路设计方法实现。

In order to improve the speed of division , a novel algorithm of radix-16 high speed divider and its ASIC implementation are presented .

本文介绍了一种用声光调制器、模拟除法器和自动锁相放大器来改进激光探针测试系统稳定性的方法。

This paper reports a technique used lor improving the stability of the laser probe consisting of an acoustooptic modulator , an analogue divider and an auto-lock-in amplifier .

基于18位自定义浮点数格式给出了改进的乘法器、除法器、加法器和比较器，并在此基础上利用已有的算法结构实现了浮点算法。

Based on the 18-bit floating number representation , the improved multiplier , division , adder and comparator is given , and then the floating arithmetic is completed .

特别在实现复矩阵求逆模块过程中找到了对传统除法器有所改进的高效的求倒数模块，使该模块的算法复杂度得到很大程度的降低。

Especially , a high-effective algorism of the reciprocal module which can greatly reduces the complexity of the module is proposed and used to implement the complex matrix inversion module .