软核

基于FPGA的交流电机控制IP软核的设计

Design of AC Motor Control IP Soft Core Based on FPGA

简单介绍了IP软核的概念。

The concept of IP soft core is introduced .

孤立词汇语音识别IP软核设计技术研究

Research on Design of Speech Recognition Soft IP for Isolated Words

形成了具有自主知识产权的40Gb/s交换IP软核。

A 40Gb / s switch IP soft-core with self-dependence intellectual property was realized .

这种带有软核微处理器的FPGA具有更大的灵活性和更强的性能。

This kind of FPGA has more flexibility and more powerful performance .

视频DSP&并行接口与Cache的软核设计

Soft Core Design of Parallel Port and Cache of Video DSP

基于SoC的IP软核设计与验证

The Design and Verification of Soft IP Based on SoC

二维离散余弦变换的VLSI实现及IP软核设计

The VLSI Implementation of 2-D DCT and Its Soft Core Design

高性能低功耗微控制器IP软核设计综述

An Overview on the Design of Microcontroller IP Soft Core with High Performance and Low Consume

本文首先根据IP软核现状，总结IP软核复用过程中可能存在的质量问题。

Firstly , this dissertation summarizes the IP soft core quality challenges according to the actuality .

4PCIIP软核的开发技术

The technology of PCI IP core

然而，IP软核在工程应用中，存在很多挑战。

However , there are a lot of challenges while IP soft core reuse in project .

基于FPGA的PCI软核模块的研究与实现

Research and Implementation on PCI Core Module Based on FPGA

研究了5Gbps~40Gbps交换技术和IP软核的实现方法。

This paper researches the implementation methods of the 5Gbps ~ 40Gbps switch technology and IP soft-core .

嵌入式8位MCUIP软核的设计

The Design of Embedded 8-Bit MCU IP Core

AES加密IP软核的研制

Research and Design of AES Encryption Soft IP Core

8位RISCMCUIP软核仿真的新方法

New Method of Simulation for 8-bit RISC MCU IP Soft Core

PCIIP软核设计技术的研究

Research on Design Techniques of PCI IP

基于嵌入式处理器软核NiosⅡ的IP复用技术

IP reuse technology and implementation based on Nios ⅱ embedded processor

AVS帧间解码IP软核的研究与设计

Research and Design of Soft-core IP for AVS Inter Decoder

EPON用户端专用芯片IP软核设计

IP soft core design of EPON client dedicated chip

功能验证和MCU软核测试技术的研究

Research on Functional Verification and MCU Soft IP Simulation Techniques

本论文详细研究了基于SoC的可复用IP软核的设计和验证技术。

This thesis mainly focuses on the design and verification of reusable IP core for SoC .

以上各模块用FPGA开发工具进行了功能仿真和时序分析，形成软核，便于移植和重用，缩短相关项目设计周期。

All of these module upper mentioned are function simulated and sequence analysis by FPGA develop tools .

在条件成熟的情况下，该软核能下载到FPGA上以产品的形式实现。

Where condition permits , it can be downloaded on FPGA and be realized as a product .

最后论文通过阵列感应井下仪平台验证了IP软核的可复用性。

The paper introduces the " Induce Array Well Logging Device " to prove the reusability of Soft-IP cores lastly .

在同步电路设计技术的基础上提出了IP软核规范化设计的具体方法；

Firstly the standard design pattern of IP core is given based on the implementation of a synchronous circuit design .

利用这个USB主机控制器软核原型系统，可以实现2个大容量USB存储设备间的便捷有效的数据交换。

This system can facilitate the data exchanging process between 2 mass storage USB devices .

快速Reed-Solomon译码器IP软核设计研究

Study on the Design of Fast Reed-Solomon Decoder IP Soft Core

它继承了硬核、软核、DSP、存储器外围I∕O及可编程逻辑。

It inherits the hardcore , soft-core , DSP , memory , peripheral I / O and programmable logic .