时钟恢复

光纤中继传输系统SAW时钟恢复滤波器

SAW Timing-Recovery Filters in Optical Fibre Repeated Transmission Systems

ATM电路仿真设备中自适应时钟恢复算法的设计与实现

Design and Implementation of Adaptive Clock Recovery Algorithm in ATM CES Equipment

基于半速率锁相环的5Gb/sCMOS单片时钟恢复电路

5Gb / s CMOS Monolithic Clock Recovery Circuit Rased on Half-rate Phase-locked Loop

一个面积和功耗优化且适用于10/100Base-T以太网的CMOS时钟恢复电路

Power and Area Efficient CMOS Clock Recovery Circuit for 10 / 100 Base-T Ethernet

DVD写时钟恢复电路系统的设计与仿真

System Design and Simulation of Write Clock Recovery for DVD Data

高速时钟恢复电路的ASIC研究与设计

Research and Design of High Speed Clock Recovery Circuit on ASIC

一种基于PLL的CBR业务时钟恢复方案

A New Clock Recovery Scheme for CBR Services Based on PLL Technique

MPEG-2编解码系统中的时钟恢复和音视频同步

Clock Recovery and Audio / Video synchronization in MPEG-2 System

MPEG的同步机制及其时序时钟恢复

Synchronization Mechanism and Time Sequence Clock Recovery in MPEG

文章实现了用于UHF频段的射频识别（RFID）标签的时钟恢复电路和反向散射调制信号产生电路。

The clock regenerator and backscatter modulator for Ultra High Frequency ( UHF ) RFID application are implemented .

本文研究了锁相环实现的高速CMOS时钟恢复电路的低噪声设计问题。

Low noise , high speed CMOS clock / data recovery ( CDR ) circuit design is treated in this thesis .

针对这个缺点，本文提出了Zigzag时钟恢复法。

To overcome this shortcoming , the Zigzag clock recovery method is proposed .

时钟恢复电路（CRC）从主放大器输出数据信号中提取出时钟信号供数据判决和后续电路使用。

Clock recovery circuit is used to extract clock from the output signal of main amplifier .

其中主要设计包括系统时钟恢复，PID过滤，TS流中节目关联表和节目映射表解码算法。

In this paper , many designs are detailed such as system clock generating , PID filtering , PAT and PMT in TS stream decoded .

突发模式PSK信号的联合载波位时钟恢复算法

A New Algorithm for Simultaneous Carrier and Bit-Timing Recovery in Burst Mode PSK Transmission

DVB-C接收机中的时钟恢复电路设计

Design of Timing Recovery Loop for DVB - C Receiver

基于0.18μMCMOS工艺的2.5GB/s时钟恢复电路设计

Design of 2.5 GB / s Clock Recovery Circuit Based on 0.18 μ m CMOS Technique

锁相环（Phase-LockedLoop，PLL）因具备独特的倍频和锁相功能而广泛应用于频率综合器、时钟恢复电路等集成电路中。

Phase-Locked Loop ( PLL ) has been widely used in frequency synthesizer and clock data recovery circuit worked as the aim of multiplying frequency and phase-lock .

本文重点通过一种改进的自适应方法对时钟恢复模块进行FPGA实现，并对其中各子模块的实现算法，原理进行了详细的阐述，然后进行了仿真。

This article proposes an improved method of adaptive clock recovery and realizes the clock recovery module by FPGA , then elaborates the algorithm and principle of its sub-module as well as simulation .

高速OTDM系统的时钟恢复技术

Clock Recovery for High-Speed OTDM Systems

论文提出一种DVB-C基带芯片中全数字时钟恢复电路的解决方案。

This paper presents an all digital timing recovery loop in a single chip for DVB-C receiver .

高速锁相环（Phase-LockedLoop，PLL）电路作为时钟恢复电路和频率合成器的重要组成部分广泛应用于现代光纤通信和无线通信中，具有非常重要的应用价值。

High speed phase-locked loop circuits as an important component of clock recovery circuit and frequency synthesizer circuit are widely used in modem optical fiber communication and wireless communication .

更高速率系统的研制目前也在开展中。时钟恢复电路（CRC）是光纤通信和许多类似数字通信领域中不可缺少的关键电路。

Clock recovery circuit ( CRC ) is the key component in the optical transmission systems as well as in the field of digital transmission .

码型转换是实现非归零（NRZ）信号全光时钟恢复的关键技术。

Pattern conversion is the key technology for all-optical clock recovery from non-return-to-zero ( NRZ ) signal .

本文提出了适用于突发模式PSK信号捕获阶段的一种快速联合载波位时钟恢复算法。

A new algorithm for fast simultaneous carrier and bit-timing recovery during the acquisition phase in burst mode PSK transmission is proposed .

根据已有的研究成果，对高速宽带时钟恢复电路进行拓展研究，提出了一种双支路无切换结构的时钟恢复电路，电路采用0.18μMCMOS标准数字工艺设计，目前正在流片的过程中。

Based on the above research , further research for high-speed broadband CDR , a dual-branch structure CDR is proposed , it is designed in 0.18 μ m CMOS process and now in fabrication .

接收模块又划分为帧起始检测单元、时钟恢复单元、帧分界符检测单元、数据译码单元、CRC校验单元、译码控制单元和长度错误检测单元等。

The decoder is also divided into start detecting , clock recover , frame delimiter detecting , data decode , CRC checkout , decoding control and length error detecting units etc.

在介绍E1相关标准的基础上，对E1线路保护电路、系统时钟恢复、信号编解码的设计与实现进行了详细的论述。

Related standards of E1 were introduced first , making a detailed discussion on the design and realization of E1 protect circuit 、 system clock recover and signal encode / decode circuits .

本论文给出了时钟恢复电路的基本原理以及采用PLL型时钟恢复电路的完整的电路设计、模拟结果和版图设计，以及将时钟恢复电路集成到光接收机后的测试结果。

The thesis presents basic principle of CRC and rounded circuit design , simulation results , layout design and testing results of a PLL type CRC , which is incorporated in a optic-fiber receiver chip .

讨论了时钟恢复电路的基本原理以及几种常见时钟恢复电路的系统构成，对最为广泛应用的锁相环（PLL）结构作了详尽的分析，包括目前它的几种设计思想。

According to principle of clock recovery , the paper also gives a detailed analysis of Phase-Locked Loops ( PLL ) among different circuit realization which is currently the most used technique , including its several design ideas .