乱序执行

文章介绍了32位RISC微处理器龙腾R2浮点处理单元的体系结构和设计，重点讨论了乱序执行、乱序结束的高性能浮点流水线设计。

This thesis proposes the architecture of the floating-point unit in a 32-bit RISC microprocessor " LongTeng R2 ", and emphatically discusses the design and implementation of a high-performance floating-point pipelining with out-of-order execution and out-of-order termination .

顺序一致共享存储系统中的乱序执行技术&模拟实现

Out-of-order execution in sequentially consistent shared memory systems : simulation results

在模拟执行和检测结果序列中，可以清楚地看到Java多线程并发程序的乱序执行情况。

In these simulation executions and model checking counter-paths , we can see how these multithreaded concurrent Java programs executed out of order clearly .

通过映射Undo操作到一个确定性的对象节点，地址空间转换的方法能很好地支持Undo操作的乱序执行，最后详细描述了若干Undo难题的处理过程。

This method could well support any Undo operation by mapping the operation to a certain object node .

基于数据流模式的乱序执行AES加密集成电路采用动态数据流结构、对并发操作串行地随机服务，通过增加顺序无关操作的数量和成批处理令牌提高不确定度。

A data flow random executing AES encryption ASIC adopted the dynamic data flow architecture and served concurrent tokens randomly and sequentially . Its uncertainty was enhanced by increasing the number of order independent operations and batch arrival of tokens .

本文使用该模型对SOMP原型系统及其任务乱序执行过程进行了仿真。

This dissertation utilizes the model to simulate the SOMP prototyping system , together with out-of-order task execution processes on it .

在对已提出的顺序、分离及乱序执行等体系分析比较的基础上，提出了VIM向量协处理器的体系结构并实现了基于VIM体系结构的向量微处理器KD-VIM-1。

Based on our study of traditional in-order , decoupled and out-of-order architectures , we proposed the VIM vector processor architecture , which adopts an improved decoupled architecture and distributed register file .

处理器要使用各种复杂技术来从串行程序中找出可以并行执行的指令，比如乱序执行、猜测执行和硬件分支预测等。

Processor utilizes many kinds of advanced technology to find the instructions , which can run in parallel from serialized program .

在综合考虑已有处理器机制的基础上，多媒体加速单元整体采用乱序执行和流水线平衡划分的策略。

Based on the overall consideration of the existing processor , out of order execution and balanced pipeline division are introduced here .

乱序执行是密码芯片设计中一种低冗余、低功耗的抵抗功耗分析攻击的方法。

The random order execution which used in cryptographic ICs is a kind of few redundancy and low power countermeasures against power analysis attacks .

因此，本文提出了一种建立包含多线程交互及线程内代码乱序执行的完整模型，并利用模型检测工具进行穷举检测的算法。

Therefore , this paper proposes an approach which builds a complete model including thread interactions and " out of order " execution in a single thread .

研究表明：乱序执行将操作的功耗差别在时间轴上进行平均，可以降低最大功耗差别。

The research concluded as the following : Execution in random order averages the power significance of the operations over the time axis and thus decreases the maximal power-distinction .