累加器

通过控制一个N位累加器累加，取其最高位，即可得到可编程时钟源。

Through controlling an N-bit accumulator and then get its highest bit to generate the programmable clock .

选择EditBox，Number并将光标移到网格上来添加这个编辑框累加器。

Select Edit Box , Number and move the cursor on the grid to add the edit box accumulator .

乘累加器在DSP算法中有着举足轻重的地位。

MAC plays a very important role in DSP algorithms .

DSP数据通路基于累加器测试的结构可测性设计

Structural design-for-testability of accumulation-based testing for DSP data path

基于DA和专用累加器的高性能DCT结构

High Performance DCT Architecture Based on DA and Special Accumulator

介绍了典型N数字小数分频器的工作过程，在此基础上分析了由级联累加器实现的积分功能。

The working process of typical N Digital fractional frequency divider is introduced and the integration function performed by cascaded accumulators is analyzed .

第五章分析了DSP的架构，并对算术逻辑单元和乘/累加器进行了验证与综合，然后在乘/累加器性能比较的基础上证明了本方案中DSP的优越性。

Chapter 4 analyzed the architecture of the master processor and did the verification and synthesis work to its sub module .

DDS由相位累加器、正弦查询表，DAC以及低通滤波器构成。

DDS consists of phase accumulator , sine ROM , DAC and LPF .

基于BCD码的模10~i相位累加器DDS设计

The DDS Design of Modulus 10 Phase Accumulator Based on BCD Code

你实际上就是在做同样的事，只不过划出了一个独立的区域，保存累加器函数，区别只是保存在对象的一个属性中，而不是保存在列表（list）的头（head）中。

You 're doing the same thing , setting up a separate place to hold the accumulator ; it 's just a field in an object instead of the head of a list .

依据Mark实际尺寸计算检测图像中Mark的半径，将累加器从三维降为二维。

Through calculation of the radius of the Mark on the test image based on practical mark size , the accumulator of Hough transform is changed from 3-dimension to 2-dimension .

DDS系统由相位累加器、波形ROM、D/A转换器和低通滤波器构成。

A DDS system consists of Phase Accumulator , Sine ROM , D / A Converter and Low Pass Filter .

我们需要写一个函数，它能够生成累加器，即这个函数接受一个参数n，然后返回另一个函数，后者接受参数i，然后返回n增加（increment）了i后的值。

We want to write a function that generates accumulators & a function that takes a number n , and returns a function that takes another number I and returns n incremented by i.

DDS采用全数字技术，主要由相位累加器、ROM查找表、DAC和低通滤波器组成。

DDS uses all-digital technology , and has the compositions of the phase accumulator , ROM lookup table , DAC and low-pass filter .

通过对频率控制字和相位累加器的控制，实现了FSK、PSK和脉冲调制等信号。

By control of frequency tuning word and phase accumulator , FSK , PSK and pulse wave is generated . 2 .

在粗略参数附近进行精确搜索，大大缩小了Hough变换累加器空间，优化了算法效率。

Then accurate searching is implemented nearby coarse parameters . This method greatly reduces the Hough transform accumulator space and optimizes the efficiency of the algorithm .

该方案利用了相位累加器的所有有效位，使DDS的性能得到提高，杂散度抑制比达到了-70dB。

This scheme utilizes all effective bits of phase accumulator address , and so can improve the performances of DDS , which has - 70 dB of spur suppression value .

同时本文采用了流水线设计和超前进位加法器来优化DDS的相位累加器模块。最后本文对DDS进行了仿真，给出了仿真结果。

Using carry look-ahead adder ( CLA ) and pipeline design optimizes the phase accumulator module . At last , this paper has presented simulation results and analysis of the results .

数控振荡器（NCO）主要包括相位累加器和波形存储器（Sine存储表）两部分，减小存储表的容量便可以节省大量的资源。

NCO mainly consists two parts : phase accumulator and waveform memory ( Sine waveform ROM ) . Reducing the capacity of ROM can save a lot of resources .

为在合理的内存开销下进一步降低算法复杂度，Hough变换的参数空间采用了5个一维累加器数组来构造。

To reduce the complexity of the algorithm with reasonable cost on memory usage , five 1D accumulator arrays are use to construct the Hough space of the Hough transform .

为了提高卷积运算的速度，采用DA分布式算法，其优点在于只需要一个查找表和一个带移位的累加器，减少了硬件资源的消耗。

In order to improve the speed of convolution , this paper adopt the DA distributed algorithm whose advantage was only one lookup table and an accumulator with shift . So it can reduce hardware resource consumption .

运算器：运算器是数据加工处理部件，它是由算术逻辑单元（ALU）、累加器、数据缓冲器等组成。

Arithmetic unit : Arithmetic unit is a data processing unit that consists of arithmetic logic unit ( ALU ), accumulator , data buffer , ect .

部分积产生器主要采用BoothⅡ型算法，大大减少了乘法累加操作中产生的部分积数目，从而提高整个乘法累加器的运算速度；

The partial product producer mainly uses the Booth II algorithm , reduced the partial product number greatly which in the multiplication accumulation operation produces , thus enhances the entire multiplication accumulator the operating speed ;

推导出三阶电荷泵锁相环的环路稳定性条件，给出了这种环路稳定性的分析方法，并采用累加器实现了三阶内插型Delta-Sigma调制器；

The analysis flow of stability is also given . And the 3-order interpolative delta-sigma modulator is realized by just using accumulator .

对于DCT的设计，采用分布式算法和专用累加器的硬件结构达到单周期8个象素的处理速度，适合高分辨率图像视频的实时处理。

First , distributed arithmetic ( DA ) and a specific accumulator are used in the design of DCT to achieve a high throughput up to 8 pixels per clock , which is suited for high definition video compression application .

本文的主要贡献就是使用Nguyen提出的高效的动态累加器，提出一个高效的常数大小的基于身份的环签名方案，并给出了严格的形式化的安全性证明。

It makes use of the efficient dynamic accumulator Nguyen [ 36 ] proposed and constructs an efficient , constant-size ID-based ring signature scheme with strict formal security proofs .

输入频率控制字经由单片机送到FPGA中的相位累加器实现对所要频率的合成，用生成的地址数据查找存在RAM中的相应单个周期波形数据，实现波形的采样合成。

Input data from single-chip produce the frequency word to the implementation of the phase accumulator in FPGA to be on frequency synthesis . Then , use the address data to search wave data exist in RAM already , implementation of the sampling waveform synthesis .

然后本文对DDS模块的逻辑设计流程进行了深入的探讨，并着重分析了ROM数据压缩后的正弦查值表与相位累加器的设计。

Secondly , this thesis thoroughly analyzes the logical design process of DDS module , and puts more emphasis on the analysis of the sine value table and the phase accumulator design which is processed by ROM data compression .

为了简化DDS系统频率控制字的计算处理，提出基于BCD码模10i相位累加器的DDS设计方案。

In order to simplify the computational processing of the frequency control words of the DDS system , this paper puts forward two designs , both taking advantages of modulus 10 phase accumulator .

文中在简要介绍了波形储存方式和累加器方式两种数字产生技术的基础上，详细讨论了基于DDFS方法产生线性调频信号的原理和实现方案。

It simply introduces two digital generation methods which are DDWS and DDFS , then detailed describes the principle and design project of LFM signal based on DDFS .