指令寄存器

为了提高JTAG接口的数据传输效率，指令寄存器和相关控制逻辑被重新设计。

To improve data transmission rate of JTAG interface , instruction register and related control logic are redesigned .

在边界扫描链设计中，采用了自定义的控制、数据、地址寄存器与指令寄存器相结合的访问ROM和RAM等相应空间方法，与原有的地址译码电路相结合，减少了硬件的开销；

The boundary scan adopts the address , data , control register together with instruction register to access relevant space , utilizes original circuit of core of DSP , decreases the cost of hardware ;

首先在驱动层的基础上实现JTAG操作接口，该接口向调用者提供读写数据、指令寄存器，读取控制器标识，设置扫描链及重启等功能函数。

Based on the driver of JTAG , a set of functions is provided including data / instruction register reading / writing , chain selecting , bypassing and resetting to the caller .

为满足3D加速引擎的实现与验证，设计搭建的图像处理平台还实现了DDR-SDRAM控制器模块、VGA输出模块、总线控制器模块、命令解释模块、指令寄存器模块及控制寄存器模块。

To meet the 3D accelerating engine to accelerate the realization and verification , image processing platform also has DDR-SDRAM controller module , VGA output modules , bus controller module , the command interpretation module and associated modules .

一个八位的指令寄存器也只能确定256种不同的操作以及对于这些操作的修改。

An 8-bit instruction register can only specify 256 different operations and variations on operations .

控制器：控制器是由程序计数器、指令寄存器和操作控制器等组成。

Control unit ( controller ): Control unit is composed of program arithmometer , instruction register and operation controller , ect .

介绍了边界扫描的基本结构、边界扫描测试操作流程、测试接口和IEEE1149.1标准规定的数据寄存器和指令寄存器，以及IEEE1149.1标准规定必须的3个指令。

The basic architecture of boundary-scan and the operation flow of boundary-scan test are introduced in the paper . Test ports , data registers and instruction registers are presented . Also , three necessary instructions that are defined in IEEE Std.

另一个办法是使用rm命令修改指令指针寄存器，然后只要输入go。

The other alternative is to modify the instruction pointer register using the rm command and just type go .

成功运行ADDI，ADD，AND和J指令，寄存器和程序计数器访问正确。

Successfully operate ADDI , ADD , AND and J instruction with correctly register and PC access .

iar-指令地址寄存器。

Iar-The instruction address register .

介绍PLC专用指令&可逆寄存器微分@SFTR指令及可逆寄存器SFTR指令，完成对3台电动机可逆顺序启动带负载控制的电工技术实验。

This paper mainly introduces the special instructions of PLC such as @ SFTR instruction of reversible register differential and SFTR instruction of reversible register . These instructions can be used to complete the experiment of ordered starting / stopping three electric motors with load .

在下面的示例中，cpuid指令采用%eax寄存器中的输入，然后在四个寄存器中给出输出：%eax、%ebx、%ecx、%edx。

In the following example , the cpuid instruction takes the input in the % eax register and gives output in four registers : % eax , % ebx , % ecx , % edx .

本文基于ARM9TDMI内核，从指令调整、寄存器分配、条件分支和循环结构等方面对汇编代码的优化方法进行了详细的论述。

This article gives a detail discussion on the assembled code optimization from instruction arrangement , register division , condition selection branch and cycle structure based on the core of ARM9TDMI .

这一描述与照片相符。指令段描述符寄存器

The description checks with the photograph instruction segment descriptor register

协作式全局指令调度与寄存器分配

Cooperating Global Instruction Scheduling and Instant Register Allocation

指令调度和寄存器分配的集成算法

Integration of instruction scheduling and register allocation

指令段描述符寄存器外部设备命令指示符

Instruction segment descriptor register peripheral command indicator

指令段描述符寄存器

Instruction segment descriptor register

这篇论文尝试解决优化编译器的后端中的两个重要的问题：指令选择和寄存器分配。

This thesis attacks two important issues in back end of an optimizing compiler : instruction selection and register allocation .

许多通用和嵌入式高性能处理器都支持谓词执行，利用谓词执行可以简化程序的控制结构，而且指令调度、寄存器分配也可以利用谓词提高效率。

Predicated execution promises to reduce control flow overhead and to enhance optimization , provided that instruction scheduling and register allocation can utilize it efficiently .

结合编译器中数据流分析，指令调度和寄存器分配的需求，进一步提出了一种基于链表结构的中间表示及构造算法。

Then , it puts forward a chain-based IR when considering the demand of data flow analysis , instruction scheduling and register allocation . At last , an algorithm is given .

ARM处理器每个异常中断对应一条跳转指令或者向PC寄存器赋值的数据访问指令。

Each exceptional interruption of ARM processor corresponds to a jump instruction or sends access instructions to the data evaluated by PC register .

可扩展矩阵计算DSP（FT-Matrix）具备其特有的包括指令集格式、寄存器设置等在内的新的体系结构特性。

Expandable Matrix Computing DSP ( FT-Matrix ) has its especial feature of architecture including instruction set and register configure .

几个SPU指令只能处理这些寄存器值中的一个。

It turns out that several SPU instructions deal with only one of the register 's values .

在SPU上，大部分指令都可以在寄存器上进行操作，就仿佛它们分别包含多个无关的值一样（因此可以对多个数据项执行一条指令）。

On the SPUs , most instructions can operate on registers as if they contained multiple , independent values ( thus the single instruction acting on multiple data items ) .

寄存器重命名是解决控制依赖和数据依赖的一种重要技术。研究并实现了一种指令调度中的寄存器重命名技术。

Register renaming is an important technique to relax the control dependence and the data dependence .

指令调度中的寄存器重命名技术

Register Renaming in Instruction Scheduling

指令集控制和寄存器管理技术是实现高性能控制处理芯片设计的重要技术。

The technology based on instruction set control and register optimization is important to realize the high performance design for micro-control unit and micro-processing unit .

所以该指令会将链接寄存器（存有返回地址）存储到调用函数堆栈框架的恰当位置。

So this instruction stores the link register ( which holds the return address ) into the proper location in the calling function 's stack frame .

729代码优化，主要从多功能指令的使用、寄存器的使用、存储区等三个方面进行研究。

729 codec mainly includes the following three aspects : utilization of multifunction instructions , appropriate use of registers , management of memory , and in particular , the prevention of pipeline contention .