特征尺寸

采用氧化物隔离双极工艺，最小特征尺寸为3μm，晶体管的fT为3.5GHz。

The use of oxide-isolation bipolar process and a feature size of 3 μ m render to the transistor an fT of 3.5 GHz .

研究结果表明：SRAM器件的特征尺寸越小，其对低能中子导致的单粒子翻转的敏感性越高。

And the dependence of low-energy neutron-induced SEU cross section on SRAM 's feature size was given .

超薄Al膜可见光光学特性与其特征尺寸的关系

The Size Effect of the Visible Optical Characteristics for Ultrathin Al Films

MEMS器件的特征尺寸范围为几微米到几毫米。

The characteristic size of MEMS components is from micron to millimeter .

特别是研究x、y定向的特征尺寸，照明分布形状可不一定是圆形的。

The shape of an illumination profile does not need to be circular , especially if X / Y feature orientation is considered .

根据出口NOx排放最低原则重新确定了燃烧室的空气配比，并借助微元法计算得到此配气比下燃烧室的特征尺寸。

Using the minimum NOx emissions principle determines the optimum air ratio of combustion chamber .

在使用API函数进行操作之前，需要解决建模相关的数学问题，如坐标系变换，特征尺寸链计算等。

Before using API functions , we need to tackle some related mathematical problems such as coordinate transformation , calculation for characteristic size .

不仅如此，随着CMOS特征尺寸的不断缩小，微电子技术的发展也将面临无法克服的瓶颈。

Meanwhile , as the CMOS size is keeping decreasing , the development of micro-electronics technology also faces the unsolvable bottleneck .

随着VLSI器件特征尺寸的缩小，对互连集成技术提出了新的要求。

New requirements are presented to interconnection integration technology because of the decreasing feature dimension in VLSI devices .

在实验基础上给出了矿用圆环链缺陷漏磁场磁感应强度B与缺陷特征尺寸的关系，同时给出了矿用圆环链缺陷漏磁场强度H的计算方法。

The relation between the magnetic induction intensity B and the characteristic size of flaw is presented . At the same time . computing method of magnetic field intensity H of flaw is given .

由于CMOS技术的进步，其特征尺寸不断减小，使CMOS技术能满足几十GHz的射频电路设计的要求。

With the progress of CMOS technology , the characteristic size is shrinking , which can meet the requirements of several ten GHz RFIC .

另一方面，使用OPC提高了工艺窗口，降低了整个芯片特征尺寸的变化，潜在地提高了集成电路的生产成品率。

Second , it increases the process latitude , decreases the variations of linewidth across a chip and could potentially enhance yield .

确定了析出相特征尺寸的对数正态分布和质量依回转半径的Maxwell分布。

The logarithm Gaussian distribution of effective size and the Maxwell distribution of particles mass with gyration radius are also constructed .

随着CMOS工艺特征尺寸的不断缩减，已经有可能利用CMOS设计Gbps速率等级的电路。

With the continuous decreasing of CMOS feature size , it has been possible to realize Gbps circuits in CMOS technology .

但是，随着集成电路的特征尺寸趋向0.18μm，互连电阻-电容（RC）延迟、功耗、串扰变得更加难以容忍。

As feature sizes in integrated circuits approach 0.18 μ m , problems with interconnect resistance-capacitance ( RC ) delay , power consumption , and crosstalk become more urgent .

随着集成电路的快速发展，Flash存储器的特征尺寸不断缩小，为了保持集成电路的性能，相应的栅氧化层厚度也不断减小。

With the rapid development of integrated circuits , Flash memory feature sizes continue to shrink . Accordingly the thickness of gate oxide should also be reduced to keep devices function properly .

在过去几十年里，CMOS工艺不断取得突破，然而其特征尺寸的进一步缩小面临着越来越严峻的挑战。

During the past several decades , CMOS technique has made great progress in breaking the feature scale of integrated circuits , while encountered with increasing challenges from many aspects .

随着集成电路（IC）技术的迅速发展，晶体管的特征尺寸已进入深亚微米、甚至超深亚微米（纳米）级。

With the rapid development of integrated circuit ( IC ) technology , the feature size of transistors has advanced to the deep submicron , or even ultra-deep submicron ( nanometer ) level .

随着半导体技术的飞速发展，作为硅基集成电路核心器件的MOSFET的特征尺寸正以摩尔定律的速度缩小。

With the rapid development of semiconductor , feature size of MOSFET as the key part of inte - grated circuits is scaling down at a speed of Moore law .

随着高集成度的超大规模电路的飞速发展，器件尺寸逐渐缩小，RC延迟成为除器件的特征尺寸外决定器件功能的最主要因素之一。

With the rapid development of high level integration of VLSI circuits , the device dimensions narrows gradually . RC delay became the characteristic dimensions in the device of the main functions of decision devices .

本文利用ANSYS对压电双晶片微驱动器结构参数与驱动性能之间的关系进行仿真分析，为微驱动器特征尺寸的选择提供了理论依据。

To prepare piezoelectric bimorph driver with good performance and adaptation to the micro-assembly , the relationships between the sizes of structure and its driving performance are simulated by Finite Element Analysis ( FEA ) software ANSYS ;

目前，器件特征尺寸已经接近纳米级，电路工作频率已经进入GHz时代，专用集成电路的集成度已经超过千万门晶体管规模[1]。

The feature dimension of device approached to nanometer level , the working frequency of circuit entered GHz times and the integration level of ASIC exceeded ten million gate transistor dimensions .

短沟道效应是MOS器件特征尺寸进入Sub-100nm后必须面对的关键挑战之一。

The Short-channel effect ( SCE ) is one of the key challenges we have to deal with when the feature size of the MOS devices is scaling down into the sub-100 nm regime .

随着VLSI电路集成密度急剧增长及特征尺寸不断缩小，互连寄生参数提取已成为集成电路辅助设计中的一个研究热点.目前，三维互连寄生电容提取的研究得到广泛关注，并取得了很大进展。

In the deep submicron VLSI circuits , with the feature size scaled down and device density increased , parasitic parameter extraction has become one of the research focuses in the field of electronic design automation .

由于器件特征尺寸的不断缩小和加工基片面积的加大，具有运行气压低、密度高、大面积均匀等优点的感应耦合等离子体（ICP）得到了人们广泛的关注。

With the advantage of low pressure , high density and sufficient uniformity , inductively coupled fluorocarbon plasma was widely studied for the decreasing in the dimension of the devices , the increasing of the substrate .

该类惯性MEMS器件由高弹性合金制作，特征尺寸在10μm~200μm，加工精度要求在±1μm，而且对加工残余应力有较高要求。

This kind of inertial MEMS components are made of high-performance elastic alloy with characteristic dimension of 10 μ m ~ 100 μ m and machining accuracy of ± 1 μ m. It also has strict requirement on the residual stress .

随着特征尺寸的持续缩小和带宽需求的增加，传统的共享总线的通信结构已经无法满足复杂片上系统（System-on-Chip，SoC）的设计要求。

As the device feature size is continuously shrinking and the bandwidth requirements are increasing , traditional shared-bus architecture will no longer be able to meet the requirements of complex System-on-Chip ( SoC ) implementations .

Sub-100-nm特征尺寸研究及干法刻蚀技术的近代发展特点

Research on sub-100-nm pattern size and development of dry etching techniques

随着半导体制造工艺的进步，器件的特征尺寸越来越小，静电放电（ESD，Electro-Staticdischarge）已经成为集成电路中最重要的可靠性问题之一。

With the development of semiconductor manufacturing process , device feature size is scaled down constantly . ESD ( Electro-static Discharge ) has become one of the most important reliability issues in ICs ( Integrated Circuits ) .

CMOS工艺特征尺寸的日益减小使得集成电路在集成度和性能方面不断获得提高；随着CMOS工艺特征尺寸的不断缩减，已经有可能利用CMOS设计Gbps速率等级的电路。

Scaling of CMOS device dimension has made great improvement in both integration and performance of integrated circuits . With the continuous decreasing of CMOS feature size , it has been possible to realize Gbps circuits in CMOS technology .