浮点加法器

三数据通道浮点加法器的FPGA实现

The FPGA Implementation of the Triple Data-path Floating-point Adder

浮点加法器IP核的VHDL设计

Design of Floating - Point Adder IP Core Using VHDL

DSP芯片中浮点加法器LOD电路的设计

A Design of LOD for DSP Floating-Point Adder

浮点加法器的VHDL算法设计

Design Arithmetic of Float Adder in VHDL

FPU中浮点加法器的设计及其内建自测试的研究

Design of the Floating Point Adder and Research of Its Bist

LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。

The LOP circuit module is described in gate level with VHDL , which has passed the logic simulation and verification . It is applied to the design of floating-point adder .

并行处理技术及其在浮点加法器设计上的应用

Paralle Processing and Its Application in Design of Floating_ Point Add Unit

快速浮点加法器的优化设计

Optimized Design of a Fast Floating - point Adder

一种快速浮点加法器的设计与优化方法

Design and Optimization of a Fast Floating Point Adder

浮点加法器的低功耗结构设计

Design of a Low Power Architecture for Floating-Point Adders

浮点加法器，浮点加漂浮植物塘协同处理农村分散生活污水研究

Research on aquatic floating plant cooperating with septic tank for rural domestic wastewater treatment

浮点加法器中进位传递问题的合并处理

The Combined Design of the Three Carry Propagation in the Floating - Point Adder

子模块包括浮点加法器、浮点乘法器、浮点除法器和三角函数器。

Sub-modules including the floating-point adder , floating-point multiplier , floating-point divider , trigonometric function device .

着重研究了整数加法器、移位器、先导零预测逻辑等浮点加法器关键部件的优化设计。

Integer adder , shifter and LZA these key parts are mainly studied and optimally designed .

实验证明这些设计的性能都比原有设计有所提高，达到了优化浮点加法器的目的。

The data and conclusions prove that these designs are better than the original ones ; the floating-point adder is really optimized .

浮点加法器是协处理器的核心运算部件，是实现浮点指令各种运算的基础，其设计优化是提高浮点运算速度和精度的关键途径。

High-Speed Floating-point Adder is a critical part in the coprocessor , which is attached to the computing basis of floating-point instructions .

基本运算单元包括浮点加法器、乘法器，并主要对浮点三角函数的硬件计算进行了设计。

The basic arithmetic unit comprises floating point adder and multiplier . Besides , the hardware calculation of floating point triangle function is particularly designed .

详细讨论了32位浮点加法器/减法器、乘法器的分级流水技术，提高了系统性能。

The pipelining technique of 32 bit floating-point adder / subtracter and multiplier is introduced in detail , which can enhance the performance of the FFT processor .

主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。

The main research area is the structure optimization of floating-point adder , which is intent to minimize the delay of floating-point addition and optimize the circuit structure .

文章从浮点加法器算法和电路实现的角度给出设计方法，并且提出动态与静态结合设计进位链的方案以及前导0预测面积与速度的折衷方法。

The paper proposes a carry chain of dynamic and static mixed circuits and a good balance between speed and area of predicting leading-zero logic circuits , consid-ering algorithm and construction of logic circuits .

基本运算单元包括18位自定义的的浮点数加法器、减法器、乘法器和除法器。

Computing units includes a custom 18-bit floating-point adder , subtraction , multiplier and divider .

传统的多输入浮点加法运算是通过级联二输入浮点加法器来实现的，这种结构不可避免地使运算时延和所需逻辑资源成倍增加，从而越来越难以满足需要进行高速数字信号处理的需求。

A multiple-input floating-point adder is usually composed of several double-input floating-point adders , and it is inevitable to increase the logic resources and processing latency , which makes it harder and harder to meet the requirements of high-speed digital signal processing .