状态寄存器

zhuànɡ tài jì cún qì
  • Status register;state register
状态寄存器状态寄存器
  1. 电台同步数据传输系统终端在收发数据时一般为透明逐bit传输,计算机并行接口包括数据寄存器、状态寄存器和控制寄存器3个端口。

    The synchronous data transmission system terminal of a transceiver always transmits bit by bit transparently when receiving and transmitting data . A computer parallel interface includes three ports respectively for a data register , a state register and a control register .

  2. 作为蓝牙模块和主机间的软硬件接口HCI,可对控制基带与链路控制器、链路管理器、状态寄存器等硬件提供统一接口。

    HCI is the interface between software and hardware of Bluetooth module and host . It offers a uniform interface to control the Baseband Link Controller , Link Manager and state register .

  3. CPU中的状态寄存器用来指示CPU的运行状态。

    State Painting The FLAGS in a CPU indicate the running state of the CPU .

  4. 根据状态寄存器的情况,主从译码器对体系中可重置IP进行复用,实现安全通讯功能。

    According to the situation of state register , principle and subordinate decoder can reuse IP to realize security communication .

  5. MAI管理设备控制器内的所有状态寄存器,并且通过8位并行数据线与设备端MCU进行数据交换。

    MAI , which manages all the control status registers , exchange data with MCU through 8-bit data bus .

  6. 数据和状态寄存器可以读取而且控制寄存器和EEPROM的值可以读取和改变。

    Data and status registers can be read out and control registers and EEPROM values can be read and changed .

  7. 采用状态寄存器的方法,减小了神经元芯片控制功能对IO引脚的依赖,提高了系统的实时性。

    Status register is introduced into design to reduce the dependence of control ability of neuron chip on IO pins and increase the real-time of system .

  8. 如果在MSR(机器状态寄存器)中可用的浮点位被禁用,将尝试执行一个浮点指令。

    An attempt was made to execute a floating point instruction when the floating point available bit in the MSR ( machine status register ) was disabled .

  9. 在调试信号时,需要查看的一些重要寄存器包括GPR、指令指针(NIP)、机器状态寄存器(MSR)、Trap、数据地址寄存器(DAR)等等。

    Important registers to look for when debugging through signals are the GPRs , instruction pointer ( NIP ), machine state register ( MSR ), trap , data address register ( DAR ), and so on .

  10. dsisr(数据存储中断状态寄存器)表示页面错误无法解决的原因。

    The dsisr ( Data Storage Interrupt Status Register ) indicates why the page fault could not be resolved .

  11. 针对这3个寄存器特点,采用计算机并行接口数据寄存器发送数据,状态寄存器接收数据和同步时钟,控制寄存器控制电台PTT。

    Taking the characteristics of the three registers into account , we use the data register of the parallel interface to transmit data , the state register to receive data and synchronize clock and the control register to control the transceiver 's PTT in this paper .

  12. 如果状态寄存器发生了变化,就意味着已经触发了一个中断。

    If there is any change in the status register , it means an interrupt has occurred .

  13. 这个线程要判断在一个循环中局部中断状态寄存器中是否发生了变化。

    This thread will keep polling whether or not any change happens in the local interrupt status register in a loop .

  14. 一种硬件交互方法,不断读状态寄存器,直到设备进入等待状态。

    A method of interfacing with hardware that involves repeatedly reading a status register until the device has reached the awaited state .

  15. 介绍了RISC单片机PIC16C57的运算部件,包括ALU、W寄存器、移位寄存器和状态字寄存器,详细说明了其电路结构、工作原理及设计特点。

    An operational unit for RISC microcontroller is described , which is composed of an arithmetic logic unit ( ALU ), W-register , shifter and status word register . The circuit structure , theory of operation and design considerations are dealt with in detail .

  16. 也就是说,现在并不通过线程状态和寄存器表示代码块(函数)。

    That is , a block of code ( function ) that now doesn 't have to be represented via thread state and registers and such .

  17. 在引入特殊的数据存储格式和状态信息寄存器组的基础上,提出一种高效的存储器管理方法,简化了编解码过程,实现了数据处理的流水线操作,也大大减少了对存储器的读写次数。

    By adopting special memory format and state information registers , an efficient memory organization method is presented , whose main characteristics include the simplification of the coding-decoding , pipelined data processing , and a significant reduction of read-write memory accesses .

  18. 在ARM状态,17寄存器是在用户模式下可见。

    In the ARM state , 17 registers are visible in user mode .

  19. 此外,蓝牙技术规范还定义了主机到控制器接口(HCI),它提供了调用下层的基带规范、链路管理协议、状态和控制寄存器等硬件的同一命令接口。

    And Bluetooth protocol also include HCI , which provide a unite command access to the lower protocols and hardware state .

  20. 程序的执行状态主要包括寄存器状态和内存状态。

    Program state mainly consists of registers state and memory state .

  21. 总线转换桥的设计包括Avalon从状态机、Wishbone主状态机和寄存器缓冲区等模块的设计工作。

    The design of bus converter bridge includes modules design Avalon slave state machine 、 Wishbone master state machine and buffer .