时钟脉冲

微处理机设计人员可以决定使所有的指令持续五个时钟脉冲。

A microprocessor designer may decide to make all instructions last five clock pulses .

该仪器能够使关键的几种脉冲时间间隔和各通道之间脉冲延迟时间具有与晶振时钟脉冲同等精度与稳定度，这些时间可以按要求事先予置扣精确测量，也可以重复再现原脉冲系列。

The interval of the key pulses and the interval between channels can be pre-set and measured accurately . These intervals are as accurate as those of clock pulses used in the system .

用EPROM构成可编程序多路同步时钟脉冲产生器的新设计方法

New Method for Designing Programmable Synchronous Multiple Pulse Generator with EPROM

另外，在抽运时钟脉冲的驱动下，输入的40Gh／s的NRZ信号光可以转换为RZ转换光，且波形较好。

With the periodical pump pulses , the input NRZ signal pulses of 40Gb / s are conversed into RZ pulses perfectly .

所以显示板工作信号频率低于20kHz，不需要外部时钟脉冲信号和电容。

Therefore , the frequency of panel controlling signal is lower than 20 kHz , and no external clock signals and capacitors are needed .

光栅信号时钟脉冲细分的误差分析

Error analysis of the clock pulse interpolation system for grating signal

文章从理论上指出了设计时钟脉冲控制器与变速时钟发生器的必要性，同时介绍了它们的工作原理和设计方法。

It also introduces their operating principles and design methods .

改进型时钟脉冲细分技术原理与应用

Principle and Application of Improvement Type Clock Pulse Subdivision Technique

从非均匀分布的信号脉冲中提取基频时钟脉冲

Base-frequency Clock Recovery from Non-uniform Optical Signal Pulses

本文对多路同步时钟脉冲产生器结构提出了一种新的设计方法。

A new method for designing the synchronous multiple pulse generator is proposed in this paper .

六个顺序脉冲发生器的设计&顺序脉冲宽度是时钟脉冲周期的四倍

The is design of six programs pulse generator & Program pulse duration is 4 times clock pulse interval

这是通过在振荡器分频链上加、减时钟脉冲实现的。

Finally , Numerical simulations are carried out to show the effectiveness of the design based on Duffing oscillator .

逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。

Logical control circuit design : this part includes the design of DFF , non-overlap clock generate and so on .

本文介绍了一种利用计算机时钟脉冲细分光栅脉冲信号相位的方法&改进型时钟脉冲细分技术。

A method for subdividing the grating pulse signal by means of using computer clock pulse is presented in this paper .

每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1。

The counter output , which represents a binary number , decreases by 1 any time the counter is triggered by a pulse .

在收到停止位之后，设备将通过拉低数据线，生成最后一个时钟脉冲来应答收到的字节。

After the stop bit is received , the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse .

但是由于计数方法本身的误差，在测量精度要求比较高或是在鉴相脉宽小于用于计数的时钟脉冲周期时，原来的测量方法就无法满足实际的测量要求。

But errors lies in the way of counter lead the bad measurement , especially when it needs high precision or the clock pulse is wider than the difference .

另采用锁相环技术实现时钟脉冲与试验电压频率同步，以保证长时间测量时φ值的准确性。

The technology of Phase Locked Loop is used to realize synchronization of clock pulse and the test voltage 's frequency in order to ensure the measurement of veracity of φ .

在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。

To use the way of put a driven circuit behind the pulser , lead through the input of count clock pulse , can avoid the irregular date on the counter during experiment effectively .

光源为时钟脉冲宽带光源，结合时分、波分和空分复用技术，采用不同包层直径光纤相熔接的应变补偿法传感头设计方案，解决温度和应变交叉敏感问题实现应变和温度同时测量。

Light source adopted clock pulse wide band source . The system integrates time division multiplexing and wavelength division multiplexing . Different cladding diameter fiber works as sensing probe . It can realize measurement of strain and temperature simultaneously .

在第11个时钟脉冲之后，如果主机并没有释放数据线，设备将继续产生时钟脉冲，直到数据线被释放（然后设备将产生一个错误）

If the host does not release the Data line after the11th clock pulse , the device will continue to generate clock pulses until the the Data line is released ( the device will then generate an error . )

文中提出了复位损失率的概念，论述了输出电压波形呈现调制状态的原因、时钟脉冲干扰的形成以及工作点参数对输出电压波形的影响，并给出了调节工作点参数的方法。

The cause of the output voltage waveform in the modulation order , the formation of clock pulse disturbance and the influence of operating point parameters on the output voltage waveform are described and the method of regulating operating point parameters is presented .

提出利用复用信号的时间不均匀性，采用主动光纤锁模激光器，直接从复用后的信号中提取出复用前的时钟光脉冲。

A scheme of using a mode locked fiber ring laser and taking the advantage of the time unevenness of the multiplexed signal to obtain the clock of the single channel from the optical time division multiplexing ( OTDM ) signal is proposed .

系统硬件部分包括GPS接收机、GPS时钟模块、脉冲峰值采集卡及工控机。

The hardware includes GPS receiver , pulse peak acquisition card , GPS clock module and industrial computer .

系统利用GPS同步时钟模块进行脉冲计数，DSP实时读取通信时间，控制时间精度在微秒以下。

The system is pulse-counted by GPS satellite synchronous clock module . DSP reads communication time in real-time in order to control the time precision under microsecond .

选用GN-80型GPS接收设备和单片微机进行电力系统状态变量同步采集终端的硬件设计，利用GPS的精确授时作为其同步时钟控制采样脉冲来实现同步采样。

This thesis selects model GN-80 GPS receiver and SCM to design the sampling device . The high accurate time service is used to synchronize the sample clock signal to realize synchronous sampling .

硬件系统包括电源电路和系统复位电路、存储器、485总线、实时时钟、水量脉冲计量电路等主要功能模块的设计与实现。

Hardware system included the design and realization of power supply and system reset circuit , memory circuit , 485 bus , real-time clock , water pulse measurement circuit , other major functional modules and so on .

设计了IRIG-B解码器，可以接收IRIG-B同步时钟信号和PPS脉冲信号，并且设计了CPLD硬件数据采集控制控制器保证采样的时间精度；

The IRIG - B decoding device can receive IRIG-B code synchronous clock signals and Pulse Per Second ( PPS ) . The CPLD hardware data acquisition controller ensures the sample time accuracy in the system .

主时钟每秒产生的脉冲数。

The number of pulses per second produced by the master clock .

在芯片的数字电路中，设计了外部RC环节配合片内环振构成的振荡电路，提供系统时钟、延迟时钟的振荡脉冲。

In digital circuits , an outer RC circuit , combined with inter ring oscillator obtain series of oscillation pulses for system clock and delay clock .