数据缓冲

在建立数据缓冲（Cache）系统一般模型的基础上，对处理器Cache和存储系统Cache的性能进行了深入分析；

On the basis of establishing a general model of data cache system , the performances of CPU-Cache and storage system cache are deeply analyzed .

数据缓冲技术的性能分析与应用

Performance Analysis and Application of Data Cache Technique

基于FPGA控制的高速数据缓冲接口技术

Interface Technology of Hi-speed Data Buffer Based on FPGA

基于FPGA的千兆硬件防火墙高速数据缓冲设计

Study on high-speed data buffer design on gigabit hardware firewall based on FPGA

MetaSearch系统中的数据缓冲机制

Data Caching Mechanism in Meta Search System

MIMO实验系统中的数据缓冲应用研究

Research on the Application Solution for Data Buffer in MIMO Experimental Systems

P2P视频点播系统中数据缓冲策略的优化

Optimize buffering strategy for P2P video-on-demand systems

PCI总线多用户数据缓冲区管理器的实现

Implementation of PCI Bus Multi-user Data Buffer Manager

Domino服务器的数据缓冲区

Data buffer for Domino servers

PowerBuilder的数据缓冲技术及共享数据窗口的应用

Powerbuilder Data - Buffer and Its Application to Share - Data window

PowerBuilder数据缓冲技术及应用

The Data Buffering Method and Application of PowerBuilder

自行设计的双口RAM控制权握手协议，为网关设备的数据缓冲提供了了解决方案。

To self-designed the dual port RAM handshake protocol for the gateway device , which provides a data buffering solution .

第一级FIFO数据缓冲电路用于存储A/D转换后的数据。

The first FIFO data buffer circuit stores the data after A / D conversion .

这种行为需要在TCP之上进行操作的面向消息的协议可以在应用层中提供数据缓冲和消息分帧机制（这可能是一项复杂的任务）。

This behavior requires that message-oriented protocols operating over TCP provide data-buffer and message framing within their application layer ( a potentially complex task ) .

基于数据缓冲区的PMP硬盘动态功耗管理策略

Data Buffer Based DPM Policy for Hard Disk in PMP

系统硬件平台主要包括基于CODEC的音频编解码模块、基于FPGA的逻辑控制与数据缓冲模块、基于ARM的嵌入式系统模块和基于DSP的协处理器模块。

The hardware platform includes the audio codec modules , FPGA-based logic control and data buffer module , ARM-based embedded system modules and DSP-based co-processor module .

充分发挥DSP处理器片内存储器容量大的特点，使用其片内数据缓冲区交替对CCD进行信号采集和数据处理；

Giving full play to the characteristic of large amount of on-chip memory , DSP acquires and processes the signal of linear CCD with the on-chip buffer alternately .

正如前面指出的，Oracle的数据缓冲区概念相当于DB2的缓冲区池。但是，DB2允许多个缓冲区池存在。

As indicated earlier , Oracle 's data buffer concept is equivalent to DB2 's bufferpool ; however , DB2 allows for multiple bufferpools to exist .

NETControl的开发流程含系统及数据库设计、DataWindow设计、DW格式文件设计、WebDataWindow控件设计、业务逻辑设计和数据缓冲区。

NET Control includes the designs of system and database , DataWindow , DW format file , Web DataWindow control , business logic and data buffering areas .

考虑到系统性能和灵活性，该平台引入数据缓冲机制，采用多种数据交换策略，以XML作为数据交换和元数据表示的标准。

In order to improve the performance and flexibility , the platform uses data caching mechanism and multiple data exchange strategies , and chooses XML as the standard for data exchange and metadata representation .

在该设置中，消息引擎对besteffort和non-persistentreliability两个质量级别的数据缓冲区使用字节为单位（默认值为320000）。

This setting is the size in bytes ( the default is320000 ) of the data buffer used by the messaging engine for the best effort , non-persistent reliability level .

该文介绍了一种基于现场可编程门阵列（FPGA）和数字信号处理器（DSP）的实时视频处理系统，此系统以FPGA为数据缓冲和逻辑控制单元，DSP为图像数据处理单元。

A real-time video image processing system is presented . In this system , FPGA is used as a main logic control unit and data buffering , and DSP processes image data .

本文介绍的是一种基于PLC的悬挂式分拣实验模型，是利用移位寄存器作为数据缓冲区：来实现顺序控制的。

This paper introduced an experimental model of hanging type transmission based on the PLC programming , and the model used the shift registers as its data buffers to realize the order control .

设置合理大小的数据缓冲区，CPU可进行局部复杂计算，实现有效的运动轨迹预测。

So far as the size of data buffer is set rationally , CPU can do more complex calculation , and so effective forecast for motion path can be fulfilled .

CAMAC双数据缓冲存储器

Double Data Buffer Memory & A CAMAC Module

分析了一种PCI总线上支持多个用户的数据缓冲区管理器电路所采用的电路结构，给出了关键点的仿真波形。

The circuit structure of a kind of PCI bus multi-user data Buffer Manager ( BM ) is analyzed in this paper , and typical simulating waveform is presented .

首先必须分配用户空间数据缓冲区和检测缓冲区，并将它们指向sgiohdr对象。

First the user space data buffer and sense buffer should be allocated and made to point to the sg_io_hdr object .

该方案硬件电路包括两路视频A/D、数据缓冲同步FIFO、DSP、FPGA、数据存储、视频合成等功能模块。

The hardware of the system includes these function blocks as following : video A / D , data buffer FIFO , DSP , FPGA , data memory and video synthesizer .

通过对关系数据库管理系统PostgreSQL的大对象数据缓冲机制的分析，提出了基于流数据的大对象数据缓冲机制。

This paper creates a new buffer strategy based on stream data with the analysis of PostgreSQL .

另外，它还具有320字节FIFO数据缓冲区。

In addition , it integrates 320 bytes of multi - configuration FIFO memory and offers two sets of FIFO data buffers for every endpoint .