内存控制器

本文详细分析了内存控制器和中断控制器的总体功能以及内部各个模块的划分，介绍了一般IP设计流程。

This paper analyzes the whole functions and separate modules of memory controller and interrupt controller and introduces the normal IP design flow .

内存控制器是影响计算机系统内存与CPU之间数据交换的重要部件之一。

In computer systems , memory controller is one of the most important control components for data exchange between CPU and memory .

不同的SoC平台中，可能包含的模块各不相同。但是内存控制器和中断控制器是必不可少的。

Although different SoC platform will have different modules , there are some necessary modules , such as memory controller and interrupt controller .

本论文对该内存控制器进行了大量的实验和测试，对实验结果的分析和对比表明，该内存控制器较前一版本的聚芯SoC的内存控制器访存性能有较大幅度的提高。

According to the experimental results on the new memory control system , the performance of it is much higher than that of the old one .

芯片上L3目录和内存控制器

On-chip L3 directory and memory controller

DDR2内存控制器的模块设计和验证平台技术研究

Modules Design and Verification Technology Research of DDR2 SDRAM Controller

内存控制器决定着计算机系统内存的最大容量、BANK数量、类型、速度、颗粒数据深度和数据宽度等重要参数，并以自动化的方式处理CPU对存储器的访问请求。

Some important parameters such as data depth , data width , maximum capacity , memory type , and bank quantity of the memory chip are decided by memory controller which automatically operates the memory access requests from CPU .

然后，结合现代DRAM存储设备的特点，提出了一种以DDRSDRAM为存储设备的新的内存控制器的结构。

And then it presents a novel memory controlling architecture with DDR SDRAM according to the characteristics of the modern DRAM storage devices .

设计了一种基于FPGA的视频实时采集系统，视频数据通过视频解码器、双口RAM、内存控制器，然后存入片外SDRAM中。

A design of real-time video acquisition system based on FPGA is presented in this paper , video data stream is stored into SDRAM via video decoder , dual-port RAM and SDRAM controller .

该小程序是一个bootloader，可以初始化附带的内存控制器，可能从某些外部源载入主程序，然后跳入主程序。

This tiny program is a bootloader that will initialize the attached memory controllers , possibly load the main program from some external source , and jump to it .

内存控制器的差错控制技术研究

Study on Technology of Error Control of Memory Controller

因此，内存控制器便成为影响内存性能发挥乃至计算机系统整体性能提升的关键因素之一。

Therefore , memory controller determines memory performance or even the overall system performance .

片上内存控制器性能评估和优化

Performance Evaluation and Optimization of On-chip Memory Controller

芯片上集成内存控制器

A memory controller on the chip

内存控制器的速度和效率，对计算机系统的整体性能有较大影响。

The access speed and efficiency have great influence on the whole performance of computer system .

第五章给出了多口内存控制器的综合与仿真结果以及系统基本调试平台的搭建方案。

Chapter 5 presented the synthesis and simulation result of multi-port memory controller , and the result of basic debug system .

各内存控制器的结构划分：由时钟产生模块、控制命令模块、指令译码模块和数据通道模块组成，对各模块的结构及实现方法进行了分析和设计。

The structure of the general-purpose memory controller divided in terms of clock generation module , control module , command module , instruction decoding module and data path module , as well as the analysis and design for the structure and implementation of each module . 3 .

SPE包括一个附加的内存流控制器（MFC）。

The SPEs include an attached memory flow controller ( MFC ) .

对于学习如何使用内存流控制器的DMA工具而言，理解这些概念将会十分重要。

This will be important as you learn how to use the memory flow controller 's DMA facilities .

与内存流控制器（MFC）进行交互的API是由mfs头文件提供的。

The API for interacting with the memory flow controller ( MFC ) is provided by the mfc headers .

包括双冗余曼彻斯特II编解码及串并转换、总线传输逻辑、终端协议和消息处理、内存及控制器及子系统模块。

The architecture of the system is composed of the encoding and decoding of Manchester ⅱ series-parallel conversion module , the bus transmission module , the remote terminal protocol and message processing module , the RAM and its controller module and subsystem module .

SPE不能直接读取主存，相反地必须通过对内存流控制器（或MFC）的单元使用DMA命令来在本地存储和主存之间导入和导出数据。

The SPE cannot read main memory directly , but instead must import and export data between the local store and main memory using DMA commands to a unit called the memory flow controller , or MFC .

分析了SDRAM芯片（MT48LC16M16A2TG-75IT）的结构和工作原理，确定了内存SDRAM控制器的内部结构和工作流程，完成了内存SDRAM控制器的控制通路和数据通路设计。

3 ) Structure and work principle of SDRAM chip ( MT48LC16M16A2TG-75IT ) is analyzed . Internal architecture and workflow of SDRAM controller is confirmed . Furthermore , its control and data path is designed .

直接内存存取控制器

DMAC Direct Memory Access Controller

基于SOPC技术的内存映射型LCD控制器设计研究

Memory mapping LCD controller design research based on SOPC technology

内存和i/o桥控制器

MIOC : Memory and I / O Bridge Controller

阐述了一种采用普通DDR内存即可实现的高速大容量报文缓存方案，并在FPGA中实现了DDR内存接口管理控制器。

A design is expatiated which can satisfy the speed and capacity of the memory only using normal DDR ( Double Date Rate ) SDRAM . And implemented the DDR memory controller in FPGA .