锁存器

提出了一种只使用单个锁存器的CMOS三值D型边沿触发器设计。

A novel CMOS ternary D type edge triggered flip flop using a single latch is presented .

因为下面进行了简化，单“阀门”装置将由一套比较器和一个RS锁存器代替。

For simplification below , a single " threshold " device will be replaced by a set of comparators and a RS Latch .

一种CMOS静态D锁存器的版图设计

Design of CMOS Static D Latch Layout

基于RT器件的数据选择器和D锁存器设计

Design of MUX and D Flip-latch Using RT Devices

首先设计出了三值ECL直接比较型D型锁存器。接着设计出了两种三值一次操作型触发器：一为三值主从存储型触发器，二为三值时钟竞争型触发器。

First , direct - comparativist ECL ternary D flip-latch with complementary-coupling structure was designed .

第三章介绍了基于FPGA的零空闲计数器及逻辑控制电路设计，利用高速的FPGA实现了由一组计数器和锁存器完成连续计数，以及对微小误差脉冲的采样。

Chapter 3 expatiates the design of ZDT counter and the logic control circuit , through which continuous count with one set of counter is realized implemented in FPGA .

具体电路由锁存器、选择器及分频器组成，以CMOS逻辑和源极耦合逻辑（SCL）实现。

The concrete circuits are composed of latches , selectors and frequency dividers . They are implemented with CMOS logic and source coupled logic ( SCL ) .

设计了DAC的数字电路部分包括锁存器、温度计译码器、电流源状态逻辑选电路等。

Several digital circuits are also used in the proposed DAC to implement such as flip-latch circuit , thermometer decoder , current select circuit , etc.

CPLD译码信号系统主要是产生译码片选信号来选通锁存器以及需要单片机控制芯片的选通信号，另外还产生一些控制信号的选通信号。

CPLD decoding signal system is mainly generated decoding chip select signals to strobe latches and the chip needed to control by microcontroller , in addition to strobing some control signal .

其主程序先完成系统初始化，再根据相应模式和档位，通过ISA总线输出数据信号并传送到地址锁存器及模拟开关。

After the initialization , according to the corresponding modes and position , the main progress sent data signals to address latch and simulate switch through ISA bus .

它由Boxcar积分器，锁存器，脉冲宽度调制器和控制信号电路组成。

It consists of a Boxcar integrator , a latch , a pulse-width modulatior and a signal control circuit .

提出了基于浮栅MOS器件的D锁存器以及D触发器的电路设计，并以寄存器和计数器为例，介绍了D触发器的应用。

D latch and D flip-flop circuits using floating-gate MOS are designed . In order to introduce the application of D flip-flop , we design the register and counter by D flip-flops .

本文介绍由R-S锁存器组成的轻触式数字密码锁的电路设计及工作原理。

Cipher-lock consists of R-S latch ; this paper introduced electric circuit design and working principle of light touched eipher-lock .

外围电路包括：保护电路、HV电路、高压产生电路、控制电路、译码电路、灵敏放大电路、八位锁存器、八位移位寄存器等。

The periphery circuit includes protect circuit , HV circuit , high voltage producing circuit , control circuit , decoding circuit , sensitively amplificatory circuit , eight bits flip-latch and eight bits shift register .

单片机2个CPU间通过双口RAMCY7C133完成数据交换，利用锁存器作为虚拟总线实现数据总线的扩展。

The two CPUs of single chip realized the data exchange through the dual-ported RAM CY7C133 ; and the latch was used as virtual bus to realize the data bus expansion .

在模拟器测控系统中，把单片机系统定义为包括：主频振荡器、看门狗和EEPROM、RS232接口、CPU、数据总线驱动器和地址总线锁存器。

In monitoring and control system of the simulator , the SCM system is defined as including : frequency oscillator , watchdog and EEPROM , RS232 interface , the CPU data bus and address bus driver latch .

改进了双模预分频器的结构，提出了一种新型集成或逻辑的SCL结构D锁存器.用一片8D锁存器实现的单片机键显接口电路

The structure of the dual modulus prescaler is optimized and a novel D-latch integrated with OR logic gate is used . Keyboard & display interface based on a 8D Flip-latch

通过对原有PFD电路结构进行重新设计，在传统D触发器PFD的基础上提出了两种新型PFD：传输门D触发器型PFD和基于锁存器的PFD。

Through redesigning the structure of the original PFD circuit and based on the traditional D trigger PFD , two new PFDs , transmission gate D trigger PFD and flip-latch based PFD were proposed .

第二个电路同样利用锁存器的正反馈特性来进行比较，不同的是使用整流的方式输出电流，在此基础上提出了一个新的多输入并行WTA电路结构。

The second one also employs the positive feedback of regenerative circuit to compare the input current . But the output current is acquired by using rectifier circuit . A new concurrent multi-input structure is also proposed .

输入端数字信号锁存器对最小宽度为40ns的写脉冲进行响应，不仅可以为内部电路提供基准电压源，同时也可以为外部电路提供10V的参考电压输出。

This convertor response to a write pulse whose least width is 40 μ s. This converter can not only offer inside benchmark voltage , but also offer outside 10V benchmark voltage .

利用555电路产生周期信号，然后对该信号进行分频，产生时序控制信号，用来控制ADC0809模块完成A/D转换，此外，使用锁存器对转换后的数字信号进行锁存以便单片机对其读入保存。

The paper firstly uses the 555 circuit to produce the periodic signal , and then provides the control signals to control the A / D transformation , the PC can read and save the data .

触发器是分接器的基本组成单元，建立时间和保持时间是影响电路速度的关键，所以减小建立时间和保持时间是触发器设计的主要目标，本文着重介绍了SCFL锁存器的设计和优化方法。

Flip-flop is the fundamental element of demultiplexer , setup time and hold up time are key factors , which influence the speed of circuit , thus the design aim is how to reduce them . In this thesis we place emphasis on the design of SCFL latches .

整个电路实现的基本单元为共栅动态负载锁存器。

This circuit employs the common-gate dynamic-loading latch as its basic cell .

作为分频器的基本单元，锁存器的工作速度直接影响了分频器的性能。

Latch is the basic unit of frequency divider .

一种基于具有回读功能锁存器的数字电路故障检测方法

Digital circuit fault detecting method based on read-back latch

该比较器包含一级预放大器、动态锁存器及时钟控制反相器。

The comparator includes a preamplifier , a dynamic latch and a clocked inverter .

在设计比较器时，采用了前置放大器加动态锁存器的结构，达到了较快的速度，并减小了反冲噪声。

A latch comparator with pre-amp has been used to reduce the kick-back effect .

高速锁存器半稳态发生概率的分析及优化

An Analysis of the Occurrence Probability of Metastable States in High-Speed Latches and Its Optimization

对于频繁的定时输出，更是可以用模锁存器控制产生定时中断输出。

It also provides a modulus latch to generate interrupt request for frequent timing outputs .

比较器是前置放大器与动态锁存器组成的开关电容电路。

It is a switch capacitor circuit which consists of the preamplifier and dynamic latch .