补码

论计算机中r进制数的表示与运算（Ⅱ）&补码

Representations and arithmetics of numbers with Radix r in computer (ⅰ) & r 's complement

给出了一种适合于用CPLD器件实现有限冲击响应（FIR）滤波器的补码算法。

The Complement Arithmetic of FIR filter fit with CPLD Devices was given .

讨论了无线局域网中的补码键控的实现过程并进行了Matlab仿真。

Practical implementation algorithms of CCK are discussed and simulated in Matlab .

基于多相补码的OFDM峰均功率比抑制

Reduction of peak-to-average power ratio of OFDM based on polyphase complementary code

基于正交全补码CDMA系统的多径信号接收技术

Multi-path signal reception techniques of the CDMA system based on orthogonal complementary codes

基于正交全补码的多载波CDMA系统

A multicarrier CDMA system based on orthogonal complementary codes

DES存在与补码及密钥选择有关的弱点，也存在设计等方面的弱点。

The DES has weaknesses that concerns complements and choice of keys , so do in design .

Costas码TH和群补码脉冲压缩雷达波形的谱分析

Spectrum Analysis of a Radar Waveform Utilizing Costas Codes TH & - Complementary Code Sets Pulse Compressing

本文提出了两类n位m进制补码网络，即网络的输入量为补码，其输出电压恰好与该补码的真值相对应。

This paper introduces two kinds of n-bit m-number complementary code network , i.e. the input of network is complementary code and the output voltage of network is corresponding with its truth .

文章追踪了CDMA系统编码领域的最新动态，并在最后给出了正交全补码的CDMA系统的多径信号接收技术。

Some new developments in CDMA system coding filed are focused on . Finally multipath signal reception techniques of CDMA system based on orthogonal complementary codes are demonstrated .

数字输出为LVDS兼容，支持二进制补码和偏移二进制两种格式。

The digital outputs are LVDS compatible and support both twos complement and offset binary format .

利用MATLAB建立了一个完整的COFDM系统，在此基础之上分别对卷积码和由RM码构成的互补码的前向纠错性能进行了仿真比较，并给出互补码的适用条件。

A complete COFDM system is constructed using MATLAB . On this basis the forward error correction comparison is made between complementary sequences and convolutional codes .

介绍了补码键控（CCK）调制解调原理和CCK解调中核心的快速沃尔什变换（FWT）算法。

The principle of CCK ( complementary code keying ) and the key algorithm-FWB-in the demodulating process is presented .

从补码的特性出发，根据CCK调制规则，采用相关解调，推导在加性白色高斯噪声信道条件下CCK调制的性能表达式。

The closed-form expressions for CCK modulation performance were derived from correlation demodulation according to the complementary code properties and CCK modulation regulation .

并且按照定点DSPs对数据处理的要求，完成了采集数据原码到补码转换程序的设计。

According to the request of fixed pointed DSPs in dada processing , the program of translating Sound Code to Complement Code is also designed .

垂直分层空时结构（VBLAST）与多码码分多址（CDMA）结合可显著提高通信系统的传输速率，而基于零相关窗互补码（LS码）的码分多址系统具有良好特性。

Combining vertical bell laboratories layered space-time ( V-BLAST ) and multi-code code division multiple access ( CDMA ) is an effective way to improve data speed , a good communication character can be obtained based on spreading codes with zero-correlation-window .

结合正交全补码编码原理，阐述了基于正交全补码CDMA系统不使用RAKE接收机，而采用自适应递归滤波器接收机的多径信号接收技术。

Combined with the principles of orthogonal complementary codes and based on orthogonal complementary codes CDMA system the multi-path signal reception techniques that adopted an adaptive recursive filter but not a RAKE receiver are described in this paper .

文中以Xilinx公司的FoundationSeries作为EDA开发软件，以原理图和VHDL语言相结合的输入方式，给出了16×16补码乘法器电路的设计实例。

The design of the hardware multiplier circuit uses Foundation Series of Xilinx Company as the EDA tools and uses the schematic and VHDL language as the input ways . A 16 multiply 16 binary complement multiplier hardware circuit is accomplished in the paper .

在缩放一模块的乘法器方案和缩放二量化结合模块中，优化了补码乘法器，减小了面积，并提高了频率。最后，完成了多标准DCT的PC仿真和FPGA原型验证。

For the multiplier method of the first scaling module and the second scaling quantization binding module , the area is reduced and frequency is increased by optimizing the complement multipliers . Finally , the PC simulation and FPGA Prototype Verification of the multi-standard DCT is completed .

阵列乘法器是在PENTIUM等高速计算机中采用的一种高速乘法运算器，据此讨论其补码阵列乘法器的设计和运算规则。

Array multiplier is one of the high_speed multipliers used in the high_speed computers , such as PENTIUM . This paper discusses the design and operation rules of the complement array multiplier .

本文介绍了IIR滤波器的FPGA实现方法，给出了IIR数字滤波器的时序控制、延时、补码乘法和累加四个模块的设计方法，并用VHDL和FPGA器件实现了IIR数字滤波。

The realization method of a infinite impulse response ( IIR ) digital filter based on FPGA is introduced . This paper proposes four blocks of IIR , which are clock control , time delay , multiply and addition , implemented IIR filter with VHDL and FPGA device .

本文提出了一个新的DDFS改进设计方法，用一个有+/-控制的D/A转换器来同时实现D/A转换和补码器两者的功能，同时还能减省补码器所需的功耗和面积。

This paper presents a new way to design DDFSs by using + / - controlled D / A converters , which perform not only the function of a D / A converter but also a complementor , then the power and area cost of a traditional complementor is saved .

快速二进制补码平方运算算法及结构

A fast algorithm and structure of the binary complement square function

关于零相关窗互补码理论界的几点讨论

A discussion on theoretical limits of zero correlation window complementary codes

二相四群补码相位调制加线性调频雷达发射波形研究

A research on four group-complementary biphase code modulation and LFM transmitting waveforms

计算机定点补码加减交替除法公式的修正

A Correct Formula of the Fixed Point Two ′ s Complement Division

多径瑞利衰落信道条件下补码键控调制性能分析

Performance analysis of complementary code keying modulation under multipath Rayleigh fading channel

纯二进制记数系统中的基数补码。

The radix complement in the pure binary numeration system .

有符号数的补码速算方法研究

Research on Fast Arithmetic About Complement of Signed Number

图示法在负数补码表示中的应用

Application of Icon - method in Negative complement representation