数字时钟

介绍在Delphi中利用Win32API路径函数设计一个具有计时功能的数字时钟的方法。

This paper presents the method that a digital clock is designed with Win32 API path function in Delphi . This clock has a function of counting time .

通过合理使用DCM（数字时钟管理单元）和BUFG-MUX（全局时钟选择缓冲器）等FPGA的特殊资源，手动搭建时钟电路，可以尽可能地减少时钟偏差对电路时序的影响。

By reasonably using the special resources in FPGA , such as DCMs ( Digital Clock Manager ) and BUFGMUXs ( global clock MUX buffer ) and manually building up a proper clock circuit , the interference to timing caused by clock skew is mostly reduced .

具备LCD数字时钟功能及闹钟功能。

With LCD data clock and alarm clock function .

论文提出一种DVB-C基带芯片中全数字时钟恢复电路的解决方案。

This paper presents an all digital timing recovery loop in a single chip for DVB-C receiver .

青海电力数字时钟同步系统建设方案探讨

Project scheme of Qinghai electric power digital clock synchronous network

基于单片机的多功能数字时钟系统设计分析

The Design of a Multifunctional Digital Clock Based on MCU

浅谈数字时钟网组网与应用

Talking About the Network and Application of Digital Clock Net

有数字时钟，日历和注意的地区，每一天。

It has digital clock , calendar and note 's area for every day .

世界时钟插件-新的模拟时钟的面孔和新的数字时钟设计。

World Clock plug-in – new analog clock faces and new digital clock design .

双闹钟数字时钟芯片设计

Design of Digital Clock with Two Alarms

一种新型通用全数字时钟匀滑技术

A Novel Universal All-Digital Clock Smoothness Technique

数字时钟信号产生技术的研究

The Research of Digital Clock Generation

大规模集成电路芯片是中等到大规模的记忆芯片，用于8位处理器、数字时钟和计算器。

LSI chips are medium to large size memory chips , 8 bit microprocessors , digital clocks or calculators .

在解决其他与后台作业相关的问题之前，我们先看看一个自制的简易数字时钟。

Before we address some other issues related to background jobs , let 's create a poor man 's digital clock .

大部这些命令的运行都很快，但现在假设您运行的是图形化桌面，并且想在桌面上显示一个数字时钟。

Most such commands run quickly , but suppose you are running a graphical desktop and would like a digital clock displayed on the desktop .

据《华尔街日报》报道，挪威广播公司正策划一档24小时的直播慢节目，记录建筑工人如何使用木头制作数字时钟。

According to the Wall Street Journal , NRK is also considering a 24-hour live feed of construction workers building a digital clock out of wood .

结合嵌入式系统课程的特点，并以数字时钟的设计为例，介绍了将建构主义教学理论应用于嵌入式系统课程教学。

Combining the Constructivism Ideology and taking the case of digital clock design , this paper presents the Application of Constructivism Ideology in Embedded System course teaching .

透过烧毁的眼睛，折磨奄奄一息的心在这模糊区之间的睡眠和清醒，他观看了脉动数字时钟滴答。

Through burned out eyes , tormented mind moribund in that fuzzy area between sleep and wakefulness , he watched the pulsating digits of the clock ticking over .

时钟以24小时制式或者带上下午指示标志的12小时制式的方式工作，可以广泛应用于实际数字时钟产品中。

The clock operates in either the 24-hour or 12-hour format with an AM / PM indicator , which can be applied to actual digital time clock products widely .

简述了一种双闹钟数字时钟芯片的设计分析，具体介绍了其中三态输入电路、可逆计数器、输出解码/驱动器等电路的设计。

This paper present a design of digital clock with two alarms and introduce some circuits concretely such as three input circuit , reversible counter and output decoder / driver .

设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。

A phase selection PLL is adopted to adjust the phase of the recovered clock , and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system .

接着，给出了遥测解调器的设计框图，分为中频单元，调频解调单元、副载波解调和数字时钟锁相单元四个部分。

Secondly , this paper provides the design block diagram of the telemetry demodulator that is made up of the IF unit , the FM demodulation unit , the subcarrier demodulation unit and the digital clock phase lock unit .

同步数字系统时钟分布及偏斜补偿技术研究

Research on the Clock Distribution Network and the Deskew Techniques in Synchronous Digital Systems

多模式数字同步时钟产生技术研究

Research of Multimode Digital Synchronous Clock Technology

同步时钟是网络同步的关键，本文对基于多模式数字同步时钟产生的系统构成、关键技术、关键技术对系统性能的影响等进行了研究。

Synchronous Clock is a key of network synchronization , this paper studies system construction , key technology based on multimode digital synchronous clock , and GPS / GLONASS , local clock , BPM short wave receiver are used .

随着片上系统（SOC）技术的发展，锁相环被广泛的应用于高性能数字系统的时钟产生。

With the development of System-on-Chip ( SOC ), phase-locked loops are widely used to generate on-chip clocks in high-performance digital systems .

文中设计的FIR可变分数延迟滤波器用于解决全数字接收机的时钟同步问题。

In this paper , the FIR variable fractional delay filter is designed and used to solve the problem of symbol synchronization of all digital receiver .

随着数字电路中时钟和数据频率的不断提高，PCB的信号完整性问题越来越突出。

With the rapidly increase of the clock frequency and data rate , the signal integrity issues of the PCB are becoming more and more serious .

几个街区之外软银（SoftbankCorp.）的一个门店外，立着一个数字倒计时时钟，也有几百名iPhone粉丝已经在排队。

A few blocks away a digital countdown clock ticked outside a Softbank Corp. store where several hundred more iPhone fans had lined up .

但这还不是全部，它也支持文本到语音和MS代理，使您的计算机更有趣，同时拥有一个具有数字和模拟时钟面临多种选择全图形显示。

But that 's not all , it also supports text-to-speech and MS Agents to make your computer more fun and also features a fully graphical display with several options of digital and analog clock faces .