延时环

运用延时环（或称环路压控振荡器）的电压-频率转换原理实现对电压信号的模数转换，提高了线性度，减小了工艺偏差；

Based on the principle of voltage-controlled oscillators ' transform from voltage to frequency , the A / D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC .

该电路设计是基于延时锁定环（DLL）原理上，采用混合信号电路设计方案来实现。

The circuit design is based on the principle of the tradition DLL in mixed-mode .

并说明了该测量仪的多项关键技术，尤其是延时锁相环加RC延迟线的两级时间内插技术；

Some pivotal technologies of the instrument are described , especially the delay locked loop and RC delay line time interpolator techniques .

本论文提出了一种利用延时锁相环产生高速低功耗列扫描信号的方法，可以大大降低CMOS图像传感器的功耗；

In this report , a new method for the high-speed and low-power horizontal scanning signal generator which by use of DLL is offered . It can greatly reduce the power consumption of a CMOS image sensor .

锁相环（PLL）和延时锁相环（DLL）是现代电子设备中最重要的组成部分之一，通常被用于时序电路和时钟产生电路中。

Phase locked loop ( PLL ) and the delay phase locked loop ( DLL ) are the most important part of the modern electronic equipment , and be widely used in the timing circuit and clock synthesizer circuit .

介绍了一种区别于锁相环（PLL）和基于压控延迟线（VCDL）的延时锁定环（DLL）、全部由纯数字电路实现的DLL电路。

This paper presents a delay locked loop ( DLL ) circuit that can be implemented with fully digital circuits . It is different from phase locked loops ( PLL ) and delay locked loop based on voltage controlled delay line ( VCDL ) .

一种新型混合信号时钟延时锁定环电路设计

A New Mixed-mode Design of DCM Clock Delay Locked Loop

全数字延时锁定环及其应用

Full Digital Delay Locked Loop and its Application

并设计了缓冲器，延时锁相环，计数器来扩大测量范围。

In addition , the buffer , delay-locked loop and counter is designed to enlarge the measurement range .

延时锁相环与锁相环相比，具有更好的稳定性，更小的时钟抖动等特点。

Delay phase ‐ locked loop compared to phase lock loop , has characteristics of better stability , smaller clock jitter .

本文叙述了长延时锁相环的研制情况和实验设备，同时也给出了通过交响乐卫星的现场试验结果。

In this paper we introduce the developmental phase and experimental equipments of long time delay phase-locked loop and also give the field test results via the satellite " Symphonic " .

电机带动LED像素列旋转，同时由单片机分时向像素列发送控制信号，并通过适当的延时，形成环场显示。

The cylindrical display mainly consists of electromotor , microchip and LED pixel lines , which are made rotating by a electromotor and receive control and delay signals from microchip .

本文根据取样数据控制系统的稳定性理论，利用z变换和修正变换方法，导出了取样锁相环和延时取样锁相环在工程设计中常用的一般稳定判据。

General stability criteria commonly used in the design of sampled phase-locked loops and delay sampled phase-locked loops are derived by using the stability theory for sam-pled-data control systems as well as the z-transform method and its modification .

一般和延时取样锁相环的稳定性研究

Stability Criteria for General and Delay Sampled Phase - Locked Loops