关键路径
- 名critical path
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基于关键路径与无死锁的DSP代码并行设计方法
Concurrent Code Design Method Base on Critical Path and Deadlock-free
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考虑信号上升/下降时间的IC关键路径算法
An Algorithm for Critical Path Extraction in IC Timing Analysis with Consideration of Slew
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上周三,德迪欧在个人网站Asymco.com上公布了对苹果2012年第二财季的预测,同时还在《关键路径》(TheCriticalPath)里详细讨论了预测情况。
On Wednesday , dediu published his Q2 2012 estimates on asymco .
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流程网络图主关键路径确定的MATLAB方法
How to Determine the critical route of process network with MATLAB
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数据结构中关键路径算法的实现Windows危急级漏洞挖掘及分析技术研究
Analyzing and Practicing for Critical Paths Calculation Research of Mining and Analyzing Technology of Windows Critical Vulnerabilities
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基于时间Petri网的供应链网络关键路径分析
Key Route Analysis Based on Time Petri Net in the Supply Chain Network
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SoC芯片中关键路径的优化方法研究
The Optimization of Critical Path in Synthesis of SoC
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微处理器内核关键路径上TLB由Data阵列和Tag阵列组成。
The TLB on the critical path of microprocessor core contains data array and tag array .
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使用MQ以从关键路径去除风险大的操作
Using MQ to get risky operations off the critical path
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FDA的关键路径动议对我国医药监管的启示
An Inspiration to Drug Administration from FDA 's Critical Path Initiative in China
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参与并完成了X微处理器全芯片的静态时序分析工作,对电路的关键路径等重要信息进行了详细分析。
We accomplished the full-chip static timing analysis of X microprocessor , and made a detailed analysis such as critical-path checking in the circuit .
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在乘法运算的实现中,采用Booth乘法器,可以大大缩短电路的关键路径,显著地提高硬件的执行效率。
Booth Recoding multiplier is adopted to further improve the hardware implementation efficiency .
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CIMAgent模拟机不但能够缩短存储设备开发的关键路径,而且可以帮助提高设备管理界面的质量。
CIM Agent simulator will not only shorten the critical path of the development cycle , but will also help quality improvement .
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讨论了供应链网络中如何选择优化路径的问题,提出采用时间Petri网对供应链网络关键路径建模的方法。
How to choose the optimal route is discussed in the supply chain network , and the time Petri net method is present .
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弱化PERT网关键路径算法研究
Research on Algorithms for Critical Path of PERT Network with Lowering Conditions
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同时,对每一个CSA单元在布尔函数级的进行重新调度,使得关键路径延时减少36%。
The CSA unit is rearranged at the Boolean level . It decreases the crucial delay by 36 % .
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许多工程都要求提交进度计划,这些进度一般都是由关键路径分析(CPA)软件制作而成的。
Thus , many construction projects have a planned project programme which has been developed using computerized critical path analysis ( CPA ) software .
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经过对实验数据的对比分析,表明文中所提并行CRC算法的关键路径延迟和硬件面积都得到了优化。
After contrast and analysis , it is indicated that both CPD and Area of the proposed parallel CRC algorithm are optimized .
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文章在静态时序分析的基础上,提出了一种利用关键路径时延信息提高FPGA分割效率的方法。
In this paper , on the basis of static timing analysis , a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay .
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文献[5]在极大代数上线性系统描述的框架下,通过关键路径研究了DEDS参数扰动对系统的影响.关键路径的计算是其核心问题。
The calculation of the critical path is the key problem of perturbation analysis in references .
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如果计划中有若干任务,每个都是50%的成功几率,全部计划的成功几率是.5N,N是关键路径上的任务数量。
If there are several tasks in the plan , each with a50 % chance of success , the overall plan 's success is . 5N , where N is the number of tasks in the critical path .
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电路综合实验表明采用本文所提出思想和方法可以有效减少MAC关键路径时延和电路门数。
Through the synthesis of MAC circuit , it validates that the ideas and methods presented in the paper do well to reduce the critical path delay and circuit gates .
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文章研究了网络计划技术在工作流模型优化中的应用,给出了基于ASD的关键路径确定算法,着重研究了过程优化中的资源优化问题。
The paper also discusses the algorithm of determining Critical Path based on ASD and the resource optimization of the product process .
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上世纪50年代末出现的计划评审法(PERT)和关键路径法(CPM)已经被证明是项目管理非常有效的工具。
It has been proved that the CPM / PERT methods arisen in the 1950s are very effective tools for project management .
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AOE网的关键路径求解算法改进及其应用
The Improvement and Application of the Key path Algorithm to AOE-net
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针对以前SRT算法的实现方法和结构,本文提出两种改进结构:一种结构可以减少SRT关键路径上的时间延迟;
As for the previously published methods and architectures for SRT algorithm , this dissertation gives out the two optimized architectures .
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关键路径查找的基本拓扑算法由于没有考虑输入信号上升/下降时间(slew),在实践中证明并不是完全正确的。
When considering the slew of the input signal , the basic topological algorithm of the critical path extraction is not always correct .
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通过采用调试接口电路的流水线映像寄存器组和特殊数据通路,可以避免在CPU关键路径上插入扫描链实现“非侵入性”的调试功能。
By using pipeline shadow registers and special data path in debug interface circuit , scan chain is no longer needed to insert in the critical path of CPU to facilitate non-intrusive debug capability .
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在一高性能超长指令字DSP处理器的设计中,通过对传统单周期读写寄存器堆的设计方案进行深入的分析和研究,优化关键路径,设计出双周期读写结构的寄存器堆。
In the design of a high performance VLIW DSP Processor , a new two-stage-access design is promoted , based on the detail analysis and study of the traditional one-stage-access design , in order to optimize the critical delay .
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对AOE网的关键路径的分析
The Analysis To Critical path Of AOE