鉴相器

首先求出鉴相器的等效传输函数，再采用Z变换。

At first , the equivalent transfer function of the phase discriminator is obtained , then the Z transformation is taken .

针对自由轴法RLC测量中因使用模拟鉴相器导致测量精度低的问题，提出采用一种基于数字鉴相的测量方法。

To free-axis RLC measuring lower precision caused by adopting analog phase discriminator , a measuring method based on digital phase discriminator is adopted .

使用DSP鉴相器的激光雷达测距系统

Lidar Distance Measurement System with a DSP Phase Detector

利用FPGA延时链实现鉴相器时钟数据恢复

A clock and data recovery method based on phase detector implemented by delay chain in FPGA

系统中的环路滤波器采用RC积分滤波器，鉴相器采用三角形鉴相特性；

In this systems , loop filter is RC integral filter and phase-detector is triangle phase-detector characteristic .

为了提高红外激光雷达测距系统的测量精度和可靠性，设计并实现了基于高速模数转换器和数字信号处理（DSP）技术的DSP鉴相器。

As a result , the lidar distance measurement system we have developed with a DSP phase detector has a precision of3 millimeters in the measuring range of2 kilometers .

用GAL构成无计数误差的倍频鉴相器

The Constitute of the None Count Error Fourfold Frequency Phase Detector with a Chip of GAL

阐述了在实时高速测量场合运用FPGA器件的优势，并给出了这种新型数字鉴相器的基本原理和具体实现过程。

The unique advantage of FPGA in the course of real time and high speed measurement is described , and the theory and realization process of phasometer are described .

在分析中，对鉴相器考虑实际中最常碰到的正弦特性，同时考虑了电压控制振荡器（VCO）的实际饱和非线性。

The phase-locked loop consists of sinusoidal phase comparator , nonlinear ratio-plus-integral filter , and voltage-controlled oscillator ( VCO ) .

主要介绍了在矿井提升机红外激光位置跟踪系统中一种新型数字鉴相器的研究方法，该方法是基于FPGA器件运用FFT算法完成的。

A new type of digital phasometer applied to the infrared laser position-tracking system of mine hoister is introduced in the paper , which is based on FPGA and FFT algorithm .

当脉冲式鉴相器中的时间常数不能忽略并具有附加简单RC网络时，得到了系统稳定的条件。

The stability condition for the system is obtained when the time constant in the pulse operated phase discriminator can not be neglected and with an additional simple RC network .

锁相环采用二阶的模拟锁相环结构，鉴相器采用Gilbert乘法器，环路滤波器采用无源滤波器，VCO采用3级环形振荡器。

The analog PLL contains three basic components : a Gilbert multiplier PD , a passive filter and a three-stage ring oscillator .

详细介绍了数字鉴相器、2s产生电路、相差检测及控制电路的电路设计和有关仿真结果。

Then the circuits and the modeling results of the digital phase detector , the 2s generating module and the phase detecting and controlling module are presented .

本课题的电路部分工作主要包括：Z向压电体高压驱动以及反馈控制电路（鉴相器、比较器、积分电路）的设计制作，开环电路参数调整、优化改进和PCB板制作。

The circuit work mainly includes : the design and fabrication of Z-direction PZT high voltage driving and feedback control circuit ; parameter adjustment , optimization of the open-loop circuit ; the fabrication of PCB board .

DMTI雷达正交鉴相器的数字校正方法

The Digital Correction Method of Orthogonal Detector in DMTI Radar

本文报道了一种电流模式高频CMOS锁相环，该锁相环由鉴相器、低通滤波器及电流控制高频振荡器组成。

This paper presents a current mode high frequency integrated CMOS phase locked loop ( PLL ) . It is composed of three parts : phase detector , low pass filter , current controlled oscillator ( CCO ) .

作者采用D-FF触发器、鉴相器和VCO构成的锁相环，研制出了码率为10.709Gbit/s的时钟数据再生模块。

Using a D-FF , phase comparator and VCO , the authors produced a 10.709 Gbit / s CDR based on PLL .

从逻辑和时序上说明了无计数误差四倍频鉴相器的结构，为使此结构满足GAL的组合逻辑结构，给出了满足GAL的逻辑方程。

The structure of none count error fourfold frequency phase detector is described in logical and time sequence . The logical equation of satisfactory GAL is put forward to meet the combination of the logical structure of GAL.

本文建议在分析复杂锁相环时，把压控振荡器（VCO）和环路滤波器之外的所有其它部件等效地看成是一个鉴相器。

This paper suggests that in the analysis of the complex phase locked loops all the components of a phase locked loop be treated , equivalently as a phase discriminator except the voltage controlled oscillator and the loop filter .

针对BOC调制信号相关函数的多峰结构容易造成捕获模糊，提出了3种相应的接收处理方法：类似BPSK的单边带处理方法、峰跳法和一种无模糊跟踪鉴相器算法。

Then presents three kinds of techniques to eliminate the ambiguity of the multi-peak of autocorrelation function to achieve BOC acquisition , which are BPSK like method , bump-jump method and one algorithm of unambiguous tracker for BOC signals .

主要讨论了低相位噪声微波锁相频率合成器的设计，并对影响其相位噪声的主要因素如环路滤波器、分频器、鉴相器及压控振荡器（VCO）分别作了分析和讨论；

This paper discusses the design of phase-locking frequency synthesis oscillator with low phase noise , and analyses and discusses the main causes for its phase noise such as loop filter , frequency divider , phase discriminator and voltage control oscillator ( VCO ) .

过零锁相即硬件锁相（PLL）由鉴相器、环路滤波器、压控振荡器及分频器组成，其原理和结构较简单，但动态性能较差，且在畸变电压输入时锁相效果变差；

The zero-crossing PLL i.e.hardware PLL , is comprised of PFD ( Phase-Frequency Detector ), loop filter , VCO ( Voltage Control Oscillator ) and frequency divider . It is really simple but poor in dynamic performance , and even worse in phase lock effect with distorted input voltage .

芯片采用吉尔伯特结构的鉴相器和交叉耦合负阻差分环形压控振荡器，总面积为115mm×075mm。

The chip size is 1.15 mm × 0.75 mm with a phase detector using Gilbert cell and a differential ring voltage controlled oscillator ( VCO ) using cross-coupled negative resistance .

微波频率合成器中的两管平衡式脉冲鉴相器

A Balanced Phase Detector with Two Diodes in Microwave Frequency Synthesizer

梯形螺纹车刀鉴相器及其集成

Lathe Tool for Cutting Trapezoid Threads Phase Detector and Its Integration

具有多电平量化鉴相器的全数字锁相环

All digital PLL with multi - level quantized phase discriminator

非线性鉴相器的引入对环路线性分析造成了困难。

Non-linear phase detector introduces difficulties for loop linear analysis .

模拟了鉴相器的工作过程。

The working process of a phase detector is simulated .

基于双向输入型鉴相器锁相环技术的光时钟恢复系统

Clock Recovery Based on Phase-Locked Loop with Bi-directly Incident Phase-Comparator

微波锁相环中取样鉴相器

Sampling Phase Discriminator in Microwave Phase & Locked Loop