进位

基于DNA自动机的串行二进制进位加法的实现

Implementation of Serial Binary Carry - Save Adder Based on DNA Automaton

Virtex~（TM）-E器件进位逻辑及其应用

The Application of Carry Logic in Virtex ~ ( TM ) - E

不存在进位传送项。

No carry-propagation takes place .

采用越级进位方式可以减小逐级进位造成的延时。

The delay due to the carry propagation through the adder stages can be minimized when a carry-look-ahead scheme is used .

N元进位反馈移位寄存器密码学性质

The Cryptological Properties of N-ary Feedback with Carry Shift Register

眼镜度数全自动测量方法（G）进位制度数

Automatic Measuring Method of Eyeglass Lens Power Degree of G-carry System

进位系统，则称A为f的一个n？

Adic system , then A is called a n ?

用FPGA实现先行进位单元阵列除法器

The Realization of Precedent Cellular Arrays Divider by Means of FPGA

提出了一种基于DNA自动机的串行二进制进位加法的实现方法。

The implementation of a kind of serial binary carry-save adders based on DNA automaton is proposed .

含有快速进位链的FPGA布局系统研究

Placement system research for FPGA with fast carry-chain

介绍了用FPGA实现先行进位单元阵列除法器的原理及方法。

The theory and method of precedent cellular arrays divider by means of FPGA are introduced .

对于一位二进制的进位加法，通过预先设计的DNA自动机模型在一个试管中以自动机的方式完成。

For one bit binary , the addition will be automatically completed in one test tube according to DNA automaton designed in advanced .

采用复序列快速傅立叶算法，结合DSP处理器中反向进位的间接寻址方式实现了采样数据的快速处理；

The device realizes real time data processing using complex sequence FFT algorithm and bit reversed indirect addressing mode in DSP .

首先提出一种并行的DNA加法算法。该算法的特点是能实现连续进位，输入输出链具有统一的形式。

The first one is a parallel addition algorithm , which can achieve continuous carry operation with a unified form to represent input and output strands .

在乘法器单元中采用BOOTH算法和先进进位加法器相结合的单元设计；

The multiplier unit adopts the BOOTH algorithm and carry lookahead adder ;

一个七进位制小数定义的连续不可微函数的Hausdorff维数

Hausdorff Dimension of A Continuous and Non-differentiable Function Defined by Septenary Decimal

在辅助寄存器单元选择一条与正向进位相反方向的进位来实现FFT算法位反序要求；

The Auxiliary register unit chooses one carry with contrary to orientation carry to achieve the FFT algorithm demand ;

针对加法器，对并行前缀结构进行了优化，将其与Ling进位和改进的选择进位模块相结合设计实现了一种新型的加法器。

Based on the optimized parallel-prefix formulation , Ling carry and modified carry-select module , a new adder is presented .

顶层进位级联CLA的算法与设计规则

Algorithm of TC ~ 2CLA ( Top-level Carry Cascade Carry Lookahead Adders ) and its design rule

浮点ALU中选择进位复合加法器的优化设计

Optimal Design of Carry-select Compound Adder in Floating-point ALU

我在跟Serena说，interested:感兴趣的interested:感兴趣的carryline:进位线BENDEL’S公司有意要接管我们。

I was just telling Serena That BENDEL 'S is interested in carrying my line . -

最近还有非线性同余法、取小数法、进位加和错位减法、广义反馈位移寄存器法和MT法等等。

The recent nonlinear congruential method , decimal fraction method , add-with-carry and substract-with-borrow methods , generalized feedback shift register method and MT method , and so on .

进位传输加法器是将所有的部分积相加产生2n位的结果，是为了生成最终结果。

Carries transmits the accumulator is adds together all partial products and produces the 2n position result for produce the final outcome .

精密时间数字转换电路有多种实现方法，本论文主要研究的是利用现场可编程逻辑器件（FPGA）中的专用进位连线来实现精密的时间数字转换电路。

There are many methods to realize precise time-to-digital converter circuits . In this paper , we introduce our research work on realizing precise time-to-digital converter circuits by using the dedicated carry chain of FPGA .

这种新型加法器是一种以半加器为基本结构单元的异步加法器，采用了并行反馈进位方式，称为并行反馈进位加法器（ParallelFeedbackCarryAdder，PFCA）。

The new adder is an asynchronous adder whose basic unit is half adder , called Parallel Feedback Carry Adder ( PFCA ) as its carry mode is parallel feedback .

采用Veriloghdl语言描述了系统的逻辑功能，超前进位结构的加/减法器提高了电路的工作速度。

Using Verilog HDL describes the logic function of the system . The carry lookahead adder or subtracter raises the working speed of the circuits .

该RSA处理器在其模乘法器中使用了CSA（进位保留加法器）结构以避免长进位链，并采用一种新型（4∶2）压缩器结构以减少面积和延迟。

A Carry-Save-Adder architecture , which is implemented by redesigned ( 4 ∶ 2 ) compressors , is used in the multiplier to avoid the long carry propagation .

余数系统（RNS）是一种并行工作机制并伴随自由进位的系统。

The residue number system ( RNS ) is a carry-free system and allows a high degree of concurrency .

三个输入端是：被加数d、加数e以及从另一个数位传来的进位数f；两个输出端是：无进位和数t及新的进位数r。

A combinational circuit that has three inputs that are an augend , D , an addend , E , and carry digit transferred from another digit place , F , and two outputs that are a ' .

提出了一种综合使用改进后的Booth编码算法、Wallace树形结构、先行进位加法器，利用HDL进行RTL级的高速运算的乘法器的设计。

This paper presents a new multiplier , which makes use of modified signed / unsigned Booth encoder , Wallace Tree and carry look-ahead adder .