芯片封装

本文首先对芯片封装及其可靠性分析方法及现状进行了概述，并对相关理论方法作了介绍。

First , the paper discusses briefly the IC package technology , the reliability analysis methodologies and the current situation of the IC package .

随着硅片直径增大，为了保证硅片具有足够的强度，原始硅片的厚度也相应增加，与此相反，为满足IC芯片封装等需要，使芯片厚度逐渐减薄。

Contrarily , the chip thickness is decreased to meet the requirements of IC package and improve the heat radiation properties of the chip .

LED芯片封装工艺中焊接缺陷研究

Research on welding fault during LED chips packaging

发光二极管采用进口大功率LED芯片封装。

LED using import LED chip for package .

基于MATLAB的芯片封装专利数据分析与预测

Analysis and forecast for the data of chip packaging patent in matlab

上海IBM芯片封装生产基地厂房的防水、防潮要求很高。

The IBM ( Shanghai ) chip coating workshop ' requirement for waterproofing and damp-proofing is very high .

基于激光电子散斑技术的IC芯片封装热可靠性分析系统研究

System Research for Analysis the Package Thermal Reliability of IC Chips Based on Electronic Speckle Pattern Interferometer

近年来，随着IC制造业的快速发展，对芯片封装技术有了更高的要求。

In recent years , as the rapid growth of IC manufacturing , the IC packaging technology suffers huge challenge .

叠层CSP芯片封装热应力分析与优化

Thermal Stress Analysis and Optimization of SCSP Chip Package

对一种先进的双悬臂梁高量程MEMS加速度计的单芯片封装工艺进行了失效机理分析。

Failure analysis is conducted for the single chip packaging process of an advanced high-range MEMS accelerometer with double cantilever beams .

未来计划开发高端存储、LED显示屏驱动芯片封装、测试项目，向超薄型新产品迈进。

In the close future , we are planning the development of the packing and testing projects of high-end memory , LED display drive chips towards the ultra-thin products trend .

阐述了MEMS的主要封装工艺和技术，包括圆片级封装、单芯片封装、多芯片组件和3D堆叠式封装等。

Moreover , some major processes package of MEMS , including wafer-level packaging , single-chip packaging , multi-chip packaging and stacked 3D packaging , etc were discussed .

测量结果表明，荧光粉远离芯片封装结构与传统封装方法相比，能够提高功率型白光LED的流明效率，并且能够降低色温。

The measurement results showed that structure that the phosphor is isolated from the chip can improve the lumen efficiency of white LEDs , as well as reduce its color temperature .

在3DMCM封装中，随着芯片封装密度的增加，对其热分析与热设计技术就显得越来越重要了。

With the developing of die package density increasing , the heat analysis and heat controlling technology for 3D MCM package becomes more and more important .

CMOS工艺的不断发展和芯片封装技术的不断进步，使得大尺寸的片外元器件成为制约整个系统体积的瓶颈。

The continued scaling down of the CMOS process and rapid improvement of integrated-circuits package techniques have made the large off-chip passive components become the bottleneck to constraint the overall system volume .

芯片封装是影响IC制造产品性能和生产效率的关键环节，芯片封装等领域的迅速发展对定位系统的行程、速度、加速度和精度的极限性提出挑战。

Die bonding plays a key role in effecting the quality and efficiency of IC production . The rapid development brings a challenge to the system in utmost stroke , speed , acceleration and accuracy .

介绍了微机电（MEMS）封装技术，包括晶片级封装、单芯片封装和多芯片封装、模块式封装与倒装焊3种很有前景的封装技术。

The technologies of MEMS packaging are introduced , including three promising technologies : wafer level packaging , single-chip packaging and multi-chip packaging , modular MEMS packaging and flip-chip bonding for MEMS packaging .

CSP是内存芯片封装技术的新概念，它的出现促进内存芯片的发展和革新，并将成为未来高性能内存的最佳选择。

CSP has developed and innovated the memory chip since it was appeared . It is believed that CSP will be the best choice of the memory with high performance .

利用有限元法研究了堆叠芯片封装（SCSP）器件在封装工艺过程中的热应力分布。

The thermal stress distribution of SCSP in packaging process was studied by finite element method .

由于SoC集成度的不断提高以及芯片封装尺寸和管脚数量的限制，传统的调试方法现在已经不能满足嵌入式软件调试的要求。

Since the SoCs have integrated more and more units , and due to the limitation of SoC 's footprint and pin numbers , the traditional debugging methods are obsolete and unable to be any help .

与单芯片封装相比，对多芯片组件（MCM：Multi-ChipModule）进行热分析时，由于存在多个热源，各个热源之间相互影响，使得热分析变得比较复杂。

Because of existing multi-powers and interacting each other , the thermal analysis of Multi-Chip Module ( MCM ) represents a much more complicated situation than encountered with single-chip packages . In this article the thermal field of several basic MCM structure are analyzed by thermal resistor net method .

研究了温度循环载荷下叠层芯片封装元件（SCSP）的热应力分布情况，建立了SCSP的有限元模型。

A finite element modeling of SCSP was performed . The distribution of thermal stress of SCSP under temperature cycle was analyzed .

本课题受到国家自然科学基金重大项目先进电子制造中的重要科学技术问题研究的资助，专门针对RFID倒装芯片封装设备中的预绑定模块进行视觉系统和运动控制集成的研究。

Dispensing technology as one of most significant process in Advanced Integrated Circuit Encapsulation ( AICE ) has become an important technique problem . The project researches the integration of the vision and motion parts of the pre-bonding module of RFID flip chip packaging machine .

COF是一种高性能、多芯片封装工艺技术，在此封装中把芯片包入模塑塑料基板中，通过在元器件上形成的薄膜结构构成互连。

COF is a high performance , multichip packaging technology in which dies are encased in a molded plastic substrate and interconnects are made via a thin-film structure formed over the components .

SCSP的焊点热疲劳寿命模拟值为1052个循环周，低于单芯片封装元件的焊点热疲劳寿命（2656个循环周）。

The simulation value of solder joint thermal fatigue life is 1 052 circulations . The thermal fatigue life of solder joint in SCSP is lower than the single chip package ( 2 656 circulations ) .

QFN是一种焊盘尺寸小、体积小、以塑料作为密封材料的新兴的表面贴装芯片封装技术。

The QFN package ( Quad Flat No-lead Package ), a new and developing technology for chip package , is a small footprint , low profile , surface mount , plastic encapsulated package with leads on the bottom .

随后对收发一体模块的结构进行了设计，探讨了SLD芯片封装技术，通过热阻理论对其进行热力学表现进行分析，使用有限元法对理论分析进行了数值求解。

Then the structure of the integrative transceiver module has been designed . The SLD chip packaging technology was discussed . Its thermodynamic performance was analyzed by thermal resistance theory . The numerical solution for theoretical analysis was given by the finite element method ( FEM ) .

高速芯片封装结构的同步开关噪声分析及抑制

Analysis and Suppression of Simultaneous Switching Noise in High-Speed Chip Package

功率器件芯片封装和静电放电失效分析

Package and Electrostatic Discharge Failure Analysis of Power Semiconductor Device Chip

步入主流领域的倒装芯片封装

Flip - Chip Packaging : Making the Move to Mainstream