标准单元

1.2μMCMOS标准单元库的开发方法

The Methodology of Developing 1.2 μ m CMOS Standard Cell Library

CMOS标准单元后仿真及其时序信息的建立

The Post-layout Simulation and Timing Information Establishment of CMOS Standard Cell

标准单元测试环境的CAD二维图形自动判别技术研究

Research in automatic evaluation technology of two-dimensional CAD graphics based on standard cell test environment

CMOS标准单元版图线网延迟的计算机时序模拟

Timing Simulation of Network Delay in CMOS Standard Cell Layout Design

一种CMOS标准单元库的评估电路设计

Design of Evaluation Circuit for a CMOS Standard cell Library

WAR文件就是WebApplicationArchive，它是打包和部署J2EEWeb应用程序的标准单元。

A WAR file is a Web Application Archive and is the standard unit for packaging and deploying J2EE Web applications .

基于标准单元的低功耗FIR数字滤波器VLSI实现

Low-power VLSI Design of FIR Filter Based on Standard Cell

VLSI标准单元通道布线的研究

Research on the channel routing order of the VLSI standard cell

GaAsASIC标准单元库建库技术研究

Research on the Technique of GaAs ASIC Standard Cell Library

本文提出了一种异步标准单元的设计流程，设计实现了两种兼容已有标准单元库标准的异步集成电路C单元，并对其进行了性能优化。

Two types of C-element are designed and implemented in this standard cell design flow . The transistor sizes of these C-elements are optimized for performance .

用模拟标准单元法设计0.8μMCMOS数模混合PLL

8 μ m CMOS mixed analog / digital PLL designs with analog standard cells

整个系统采用标准单元设计方式和Top-Down自上而下的设计方法。

The design is accomplished using Top-down design flow and standard cell library method .

本文设计的近阈值标准单元包进行ASIC设计。

Near-threshold standard cells in this thesis are designed based on ASIC design .

采用标准单元法的ASIC设计实例

An Example of ASIC Design Using Standard Cells

MOS电流模逻辑标准单元设计方法

Design method of MCML standard cell

此技术可以有效地应用于其他CMOS或SOI工艺标准单元库的开发。

The flow technology can be effectively applied to standard library development of other CMOS and SOI processes .

本文介绍了在兼容宏单元的标准单元模式下进行自动布图设计结果的面积预测及缓冲单元（Buffer）调整的方法。

The method of area prediction and buffer cells adjustment for automatic layout design result are introduced in tne model of standard cell compatible macro cell .

过滤器逻辑结构的模块化特别适宜用标准单元法来实现ASIC（专用集成电路）的版图设计。

The modularization of filter logical architecture is especially suitable for layout design of ASIC with standard cell .

哪些因素在推动着FPGA技术的普及，以至于FPGA在许多应用中正在替代门阵列和标准单元ASIC？

What 's fueling the popularity of FPGA technology to the point that it 's now replacing both gate array and standard-cell ASICs in many applications ?

本文提出在ASIC综合技术中基于标准单元库的多级逻辑函数分解技术。

The decomposition of multilevel logic functions based on standard cell libraries used in ASIC synthesis is presented in the paper .

标准单元库是ASIC设计的基础，它的质量和性能对ASIC设计来说至关重要。

The standard cell library is a foundation to ASIC Design , its quality and performance is vital to ASIC Design .

实验结果表明，这种标准单元库能够很好地起到防DPA攻击的作用。

The experimental results demonstrate that the DPA-resistant standard cell library can counteract DPA attacks effectively .

芯片版图的再设计采用了3μm的P阱硅栅单层金属CMOS版图设计规则，对逻辑组合电路部分的版图采用了标准单元的设计，从整体上缩小了芯片的面积。

The chip layout redesigns adopt 3 μ m P-well silicon gate single metal CMOS layout design rules . Logic combination circuit layout adopts standard cell design which reduces chip area on the whole .

本文主要论述FPGA（现场可编程门阵列）至其它ASIC实现方式，如门阵或标准单元的设计转换；

This paper deals with the design conversion of field programmable gate arrays ( FPGA ) to other ASIC implementations . such as gate arrays and standard cells .

本文采用通用的数字ASIC设计流程，在仅使用已有标准单元的情况下，提出了一种新的基于FIFO的异步包装。

A new FIFO-based asynchronous wrapper was proposed , which implemented using only standard cell and optimized in a standard digital ASIC flow .

下面的图展示了LEF标准单元和形状类似的布局数据。

The following figure shows a LEF standard cell with shapes similar to layout data .

采用标准单元方法的集成电路设计系统是一个用于专用集成电路（ASIC）设计的自动布图系统。

This IC design system applicable to the standard cell method is an automatic layout system used for designing Application Specific ICs ( ASIC ) .

本文综述了基于标准单元库和FPGA的成熟的工艺映射方法，概述了高级综合系统中工艺映射的主要任务、研究现状和发展。

In this paper , we summarize some mature methods for standard-cells library and FPGA technology mapping , and then introduce the tasks of technology mapping in high-level synthesis and its present existing situation and development .

SoC集成电路有多种实现方法，通常我们采用基于标准单元半定制设计方法，除此之外，还采用全定制的设计方法，FPGA设计方法，他们各有优缺点，在不同场合有不同的应用。

The realization method of SoC is variety . Generally It is based on standard cell semi-custom design approach . In addition , it also can use full-custom design flow and FPGA design flow .

ADC采用SAR结构，其中DAC的版图以单位电容和相应开关为标准单元库进行设计。

ADC adopted the successive approximation register algorithm . The layout of DAC was on the basis of the standard cell , which contained the unit capacitor and the corresponding switch .