时钟频率

以DDS为核心实现对时钟频率输出的精密控制。

Achieve precise control of clock frequency through DDS . 3 .

由于FPGA并行执行的机制，使得它可以在较低的时钟频率下也可以很好的实现实时视频图像处理。

Because of the parallel mechanism , it is good at processing real-time video image at a lower clock frequency based on FPGA .

这台机器的时钟频率为1.6千兆赫。

This machine has a clock speed of 1.6GHz .

嵌入式系统低功耗设计的一种方法&控制MCU时钟频率

One Method of Low-Power Embedded System Design-Control MCU Frequency

第2个参数指定的是像素时钟频率（单位为MHz）。

The second parameter specifies the rate of the pixel clock in megahertz .

有一点需要注意：如果没有CPU任何活动，某些处理器会降低时钟频率。

It should be noted that some processors will step down clock speeds if there is no activity on the CPU .

引入逆向P码发生器，实现了对驻留的接收数据进行快速逆向搜索，可以将捕获系统的时钟频率提高5～10倍甚至更高；

The AntiP code generation is designed to implement the reverse search of code phase , which increases the clock of acquisition system 5 to 10 times or more than traditional structure .

进行静态时序分析后，FPGA系统中发送部分和接收部分运行在相应时钟频率下具有足够的时序余度。

After static timing analysis , FPGA system still have sufficient timing margin in the corresponding clock frequency when running sending and receiving parts .

文中给出了整个IP核及其各模块的综合和仿真结果，IP核的最高运行时钟频率可以达到127Mhz。

The thesis gives the synthesis and simulation results of IP core and its modules as well . The IP core reaches an operating frequency of 127 MHz .

FPGA是一种可编程器件，具有速度快，时钟频率高，内部时延小，开发周期短，内部资源丰富等优点。

FPGA is a programmable device , which is fast , high frequency , low inner delaying , short develop cycle , rich logic resources , etc.

主要工作包括：围绕处理器内核可动态改变时钟频率和工作电压的特点，在嵌入式Linux系统中实现可变电压技术；

The main work includes : adding dynamic voltage scaling to embedded Linux , based on the characters of processor , which can dynamically change its speed and voltage ;

在时钟频率较高的MCM中，可采用终端匹配技术来有效的抑制互连线上的反射噪声。

In the higher clock frequency MCM , terminal-matching method can be used to control interconnection reflection .

跟传统的单核CPU相比，多核CPU带来了更强的并行处理能力、更高的计算速度和更低的时钟频率，并大大减少了散热和功耗。

Comparing with the single core , multi-core CPU brings us more powerful parallel processing ability , higher computing speed , lower time frequency and low cost .

并将仿真结果同Matlab仿真结果进行了比较，仿真结果和比较结果验证了本文中所设计的硬件结构的正确性和可行性，系统可以在较高时钟频率下实时地对图像进行小波变换。

Compared with Matlab simulation , The result proves that the proposed hardware structure is proper and feasible for the highly realtime processing image and system can work at high frequency .

在种类众多的总线类型中，拥有33.3MHz时钟频率、32位数据线宽度和最高可达266MB/s数据传输率的PCI总线以其优越的性能脱颖而出，成为当前最流行的总线标准。

32-bit data bus ; 266MB / s maximum data transfer . These features make it the most popular bus standard among various buses in existence .

虽然CPU的时钟频率下降，内存和I/O带宽并没有减少，使相当均衡的表现要实现跨越大多数应用。

While the CPU clock rates are down , memory and I / O bandwidth wasn 't reduced , allowing fairly balanced performance to be achieved across most applications .

在深亚微米时代，随着设计规模变大，时钟频率越来越高以及工艺尺寸的减小，IC物理设计面临着诸多困难。

In deep submicron era , IC design in physical design has more and more challenge , with the increasing design scale , faster clock frequency and minimizing process dimension .

采用直接数字合成（DDS）技术，提出了新的基带回波功率谱的合成方法，显著降低了基带信号合成的时钟频率和数据存储容量。

A new synthesis method of baseband echo power spectrum , which adopts Direct Digital Synthesis ( DDS ) technology , reduces greatly the clock rate and data memory .

为了提高AES加解密模块的时钟频率和数据吞吐率，采用了内外混合流水线的策略；同时在分析了系统的应用需求后，采用AES加解密模块复用的方案来减小硬件面积。

This system uses encryption and decryption reuse to decrease the area of AES module , uses inside and outside double pipeline to increase the clock frequency and throughput .

当CPU时钟频率为100MHz时，DMA单通道能达到的16位最高传输率为25M/s。

When a processor operates with a CPU clock rate of 100 MHz it can support a maximum of 25M 16-bit transfers per second .

英特尔的Corei5和Corei7运行，远低于其热和电的限制，使涡轮推动的“超频”的CPU时钟频率和速度。

Intel Core i5 and Core i7 operates well below its thermal and electrical limits , allowing the Turbo Boost to " overclock " the CPU clock frequency and speed .

验证结果表明，该MCU的最高时钟频率和指令执行效率等指标均优于MCS-51的五倍以上。

It is shown from FPGA verification and computer simulation that the MCU core 's maximum clock frequency and instruction efficiency are five times higher than those of MCS-51 chips .

技术继续发展，硬件的趋势非常清晰；Moore定律表明不会出现更高的时钟频率，但是每个芯片上会集成更多的内核。

Going forward , the hardware trend is clear ; Moore 's Law will not be delivering higher clock rates , but instead delivering more cores per chip .

100MHz时钟频率下的最大数据吞吐率可达128Gbit/s。

The maximum data throughput will reach 1.28Gbit/s at 100 MHz system clock .

参考时钟源送到FPGA中做采样处理，CPU根据FPGA中计数结果，动态调整OCXO输出时钟频率。

The reference clock source is sent to FPGA in order to do sampling process . CPU adjusts the output clock frequency of OCXO dynamically according to the result of counter in FPGA .

首先分析了时钟频率偏差对OFDM子载波造成的相位旋转和载波间干扰，并针对试验系统进行偏差测试，验证了理论推导的结论。

First it analyzes the phase rotation and inter-carrier interference of the OFDM sub-carriers caused by the clock frequency deviation , and carries on a deviation test for the trial system which verifies the conclusions of theoretical derivation .

这种信号处理电路的主要优点是具有柔性，只要对CCD器件工作时的时钟频率加以变化，就可以适用于多种测量系统，具有较大的实际工程应用价值。

The main advantage of the design is its flexibility . If The technology can be used to many kinds of measuring system by changing the clock frequency when CCD is working , and has a great value for engineering application .

用1μMCMOS单元库进行综合，在50MHz时钟频率下，电路规模为3000门左右。

The circuit is synthesized by 1 μ m CMOS cells library . It costs only 3000 gates when it works in 50 MHz .

除了存储器之外总共大约有170000个门电路，并且时钟频率达到了100MHz。

The total gate count excluding memory is about 170 000 gates and the clock frequency is 100 MHz .

应用的多样性要求PLL能够提供不同的输出频率，随着时钟频率的不断提升，系统对于锁相环的抖动性能越来越敏感。

The diversity of applications has also led to require diversity in operating frequencies of PLL . As the increasing of system frequency , the system performance is much more sensitive to the jitter of the clock .