时钟信号

主芯片通过SSC接口与FPGA进行通信，控制FPGA的时钟信号，FPGA工作于从模式，控制FPGA的时钟信号。

The main chip control the clock signal of FPGA , the FPGA works in slave mode .

在这种情况下，内侧副韧带是内存时钟信号，而MDA是内存数据信号。

In this case , MCL is the memory clock signal , while MDA is the memory data signal .

异步中断是由其他硬件设备产生的，可以在CPU时钟信号的任意时刻到来。

Asynchronous interrupts are generated by other hardware devices at arbitrary times with respect to the CPU clock signals .

在多FPGA设计中，时钟信号的传输延时造成了FPGA间的大时钟偏差，进而制约系统性能。

In multi-FPGA designs , the delay of clock transfer causes a huge clock skew between FPGAs and therefore undermines the system performance .

在高速数据传输接口中，由于数据窗缩小以及传输路径不一致，造成数据和时钟信号在FPGA的接收端发生位偏移和字偏移。

Data may arrive at the FPGA receiver with channel-to-channel bit skew and word skew due to different trace length and smaller data window .

在串行数据输入（DI）或输出（DO）时使用的时钟信号。

Used as the synchronization clock when inputting ( DI ) or outputting ( DO ) serial data .

在二值单闩锁结构边沿触发器的基础上，把利用时钟信号竞争冒险的思想应用于三值电路中，提出了基于CMOS传输门的二值D型时钟信号竞争型边沿触发器。

Then this principle is adopted in ternary circuit , a new ternary D type edge-triggered flip-fiop based on CMOS transmission gate is proposed .

PLL系统被广泛的应用于各种高速数字系统中，来产生低抖动片上时钟信号。

Phase-locked loops ( PLLs ) are widely used in high speed digital systems to generate low jitter on-chip clocks .

采用基于GPS时钟信号，通过NTP协议实现不同平台间校时的方法，提高了数字电视系统的整体安全可靠性。

Based on GPS signal , through NTP protocol realize different platform time checkout , this way improves the security of DTV .

着重分析采用直接数字合成（DDS）技术产生任意频率时钟信号的方法，实现数据发生器以任意码率输出数据；

Direct Digital Synthesize ( DDS ) is used to generate clock signal at any frequency so that data generator can output data at any rate .

设计了一种新的产生RSFQ时钟信号的电路，并利用WINS软件对电路进行了模拟。

A new type of timing pulse generator is designed and simulated using WINS software .

基于LiNbO3调制器的高速时钟信号的提取

High Speed Clock Recovery Based on LiNbO_3 Modulator

以SDRAM为基础采用DLL技术，并对时钟信号进行两次抓取资料，形成DDR技术。

Based on SDRAM , we adopt DLL technology and catch information twice on time signal , and it is so-called DDR technology .

利用DSP强大的数字信号处理能力，为系统提供精确的控制和时钟信号，并能快速准确地处理采集数据，达到高速测量的目的。

It can achieve the purpose of the high speed measurement to provide precise control signal and a clock signal and process acquisition data rapidly and accurately by the powerful digital signal processing ability of the DSP .

本文提出一种基于数字电路架构的IR-UWB信号发生器，可以通过外加时钟信号产生GMPUWB信号。

Based on digital circuit architecture , this paper designs a IR-UWB signal generator , which can generate GMP UWB signal with inputting the clock signal .

该ADC要求采用1.8V模拟电源供电及差分时钟信号，以便充分发挥其工作性能。

The ADC requires a1.8 V analog voltage supply and a differential clock for full performance operation .

系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。

The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake .

利用DCM产生的具有精确占空比的时钟信号，给出了其在DDR总线数据传输中的应用，并给出了仿真结果。

The clock signal with precise duty cycle produced by DCM is used in the bus data DDR transmission . The simulation results are also given .

而作为锁相环的关键部件，压控振荡器（Voltage-ControlledOscillator，VCO）产生锁相环的输出时钟信号，其特性直接决定锁相环性能的好坏。

While as the key unit , voltage-controlled oscillator ( VCO ) generate the output clock signal of PLLs , and its identity directly decide the capability of the PLLs .

设计的VCXO能输出高稳定度、振幅恒定的时钟信号。

The VCXO circuit can put out clock signals with high stable frequency and the constant amplitude .

AHB总线控制器采取自顶向下的设计方法，分为仲裁器，译码器，选择器，寄存器，门控时钟信号产生等模块。

AHB bus controller to take top-down design , divided into arbitration , decoder , mux , register , gated clock signal modules .

预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。

The preprocessor can extract clock information from NRZ data stream , which consists of a delay cell , a multiplier and a narrow-band filter .

该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。

To erase the bootless power dissipation of the redundant leap of the clock , this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique .

本文介绍了用于该测试的高精度信号发生器的实现方案，该电路能够产生抖动（Jitter）小于23.623ps的脉冲信号和抖动小于12.265ps的40.000MHz时钟信号。

This paper introduces the design of a high accurate signal generator circuit for this testing , which can generate pulse signal with the jitter less than 23.623 ps and clock signal with the jitter less than 12.265 ps.

该时钟源可输出500MHz或外接信号源频率的两路正交差分ECL时钟信号。

The system is capable of outputting two differential ECL signal s of 500 MHz or the frequency from some signal generator .

设计了IRIG-B解码器，可以接收IRIG-B同步时钟信号和PPS脉冲信号，并且设计了CPLD硬件数据采集控制控制器保证采样的时间精度；

The IRIG - B decoding device can receive IRIG-B code synchronous clock signals and Pulse Per Second ( PPS ) . The CPLD hardware data acquisition controller ensures the sample time accuracy in the system .

同样通过降低电压和频率，C1E尝试比传统C1状态（只会停止时钟信号）提供更大的电能节省。

C1E tries to provide more power savings than the traditional C1 state ( which only halts the clock signal ) by also lowering the voltage and frequency .

首先，我们对像素级A／D转换型图像传感器的系统工作原理进行了分析，是由像素阵列、时钟信号产生器和SAM（顺序读写存储器）三部分构成的。

The first , we analyze the system operation theory of CMOS image sensor with pixel level ADC ( A / D Converter ) . It is made up of three sections : pixel array , clock signal generator and SAM ( Sequential Access Memory ) .

系统在实现过程中，利用FPGA内部时钟信号clk同步化异步信号，不但充分发挥了FPGA的内部资源，且避免了因信号毛刺可能产生的电路错误。

In the process of implementation , not only FPGA 's inner resources were fully made use of , but also the circuit mistakes caused by signals ' burrs were avoided using FPGA 's inner clock signal to make the asynchronous signals synchronized .

本文介绍了光时分复用技术（OTDM）的特点和现状，并从OTDM超短脉冲源和帧时钟信号提取2个方面分析了OTDM技术走向实用化的2个关键技术。

The characteristic and actuality of Optical Time Division Multiplexing ( OFDM ) is introduced in this paper The two available key techniques about OTDM are discussed based on ultra-short pulse source and frame-clock extraction .