多层布线

适用于多层布线作细线导体，也适用于气敏传感器作电极和电极引线的焊接材料。

Applicable for thin multi-layer wiring conductor , also apply to gas sensors for welding electrodes and electrode-lead material .

ULSI多层布线中Cu的CMP技术

CMP of Copper for Multilevel Metallization of ULSI

MCM多层布线基板的可靠性研究

Reliability Research on Multi layer Substrate of MCM

ULSI制备中多层布线导体铜的抛光液与抛光技术的研究

CMP Study of Multilayer Wiring Conductor Copper in ULSI Manufacturing

ULSI铜多层布线中钽阻挡层CMP抛光液的研究与优化

Study and Optimization of CMP Slurry Used to Tantalum Barrier Layer of Copper Interconnection in ULSI

方法首先对零件库加以扩充，并研究MCM多层布线基板设计等问题，为布局布线做准备。

Methods The library is developed firstly , then an eight-layer substrate is designed which is the basis of MCM placement and routing design .

针对重叠端口通道的多层布线模型，提出了一个优化通道内dogleg数目的算法。

An algorithm is presented to minimize the dogleg number of the multi layer terminal stacked channel routing results .

低温共烧陶瓷（Low-TemperatureCo-firedceramic，LTCC）技术是共烧陶瓷多芯片组件（MCM-C）中的一种高集成度多层布线封装技术。

Low-Temperature Co-fired Ceramic ( LTCC ) technology is one type of Co-fired ceramic multi-chip module ( MCM-C ), which is a high-integration and multilayer - printed packaging technology .

然后通过一种自适应迭代策略，将多层布线转化为H-V布线层对序列来处理。

Then a multi-layer routing problem is converted into a sequence of two-layer routing problem by self-adaptive iterative strategy .

根据多层布线铜CMP要求，采用弱氧化剂、强络合剂、非离子型的实验特点达到铜的CMP的高速率、合适的选择性、无污染的要求。

To meet the requisition of copper CMP in ULSI , the experiment specialty , which are weak oxidant , strong complex and non-metal ions , achieved high CMP rate , appropriate non-contamination .

在多层布线的线段－相交图模型基础上，利用Hopfield人工神经网络理论，通过把通孔数目这个优化目标与Hopfield网络能量函数相联系的方法来解决多层布线通孔最小化问题。

A new approach to multi layer constrained via minimization is presented . The new approach based on the segment crossing graph model and Hopfield neural network theory . The minimization is achieved by correlating the number of vias with the energy function of Hopfield networks .

多层布线有约束通孔最小化的遗传优化算法

A Genetic Optimization Algorithm of Constrained Via Minimization for Multi Layer Routing

硅基多层布线集成组装技术

Integrated Package Technique of Multilayer Wiring on Silicon Based Board

应用于蓝牙技术发展的LTCC&AlN多层布线工艺

LTCC AlN multilayer technology applied to development of bluetooth technology

性能驱动的多层布线有约束分层及其神经网络求解方法

Performance-Driven Constrained Layer Assignment in Multi-Layer Routing Using Neural Network

芯片级多层布线关键技术研究

The Research on Key Technologies Used in Chip-level Multi-layer Routing

算法采用单步的区域多层布线策略，实现资源的合理分配；

The router adopts single-phase multi-layer area routing and achieves the optimized routing resource .

多层布线介质表面用中高阻电阻浆料的研制

Development of Resistive Pastes with Middle and High Resistivity Used for Multilayer Wiring Dielectric Surface

多层布线受复杂版图设计规则约束，简单直接应用迷宫布线算法，或者无法获得优化的结果，或者无法满足设计规则。

It cannot straightforward acquire optimal result or satisfy the sophisticated design rule for multilayer situation .

薄膜多层布线工艺分析

An Analysis of Thick-film Multi-layer Technology

设计规则驱动的多层布线算法

Design Rule Driven Multilayer Routing Algorithm

一种有约束的多层布线通孔优化算法

Optimization of Constrained Multi-layer Routing Algorithm

文章提出了一种采用遗传算法的多层布线有约束通孔优化算法。

In this paper , we presented a genetic algorithm for constrained via minimization problems in multi-layer routing .

最小特征尺寸在0.35μm及以下的器件，多层布线的每一层都必须进行全局平面化。

For the IC character measure lower than 0.35 μ m , every interlayer metal must be global planarization .

虽然随着工艺的进步，我们可以在多层布线以最大限度的减少面积。

With the development of the technologies , we could use several layers to layout stacked structure in order to reduce the total area .

该模块采用多层布线的叠层结构，电路设计紧凑，减小了分布参数，使电路工作时的电压和电流应力明显减小，从而提高了电路的性能，并降低了电磁干扰。

A multilayer structure is adopted resulting in compact circuit layout and reduced parasitic parameters , the voltage and current stresses on switches as well as the EMI of the circuit are significantly reduced .

包括激光金属平坦化，激光载带自动键合，激光多层布线和多芯片互连以及激光掩膜版和芯片图形缺陷的修复。

Tire recent advance on applications of laser processing in VLSI is presented with the emphasis on metal planarization , tape automated bonding , multiple layer metal electrods , multichip interconnection and mask or chip failure repair .

随着集成电路的高速发展，传统的微米级导电浆料已不能满足低温烧结和多层布线的要求。

With the rapid development of integrated circuits , the traditional conductive pastes in which the sizes of the functional phase are in the range of micros can not meet the demands for low-temperature sintering , narrow line widths and multi-layer boards .

研究了导电相、玻璃相和添加剂对多层布线表面电阻的方阻、温度系数和稳定性的影响，分析了介质层与电阻层之间的相互作用而导致电阻阻值变化的机理。

Effects of conductive and glass phases as well as additives on surface resistivity , it 's temperature coefficient ( TCR ) and stability of multilayer wiring dielectric surface are researched and mechanism of resistance floatation due to interaction between dielectric and resistive layers is analyzed .

多层VLSI布线通孔最少化的遗传算法

A Genetic Algorithm for Via Minimization in VLSI 's Multilayer Routing