处理器结构

本文提出一种基于动态二进制翻译优化的可扩展处理器结构VISA。

This paper presents VISA , a scalable processor architecture based on dynamic binary translation ( BT ) and optimization .

清单中的每个程序集都是按照程序集的名称、版本号和处理器结构指定的。

Each assembly is specified in the manifest by its name , version number and processor architecture .

具有显式线程支持Java的可实现的处理器结构

Scalable Processor Architecture for Java with Explicit Thread Support

基于多片DSP处理器结构的高速加密卡

A Kind of High Speed Encrypt Card Based On Multi-DSP Processor Structure

基于CDMA网络的多处理器结构视频监控系统

Multiprocessor Video Surveillance System Based on CDMA Network

基于CPLD和多处理器结构的控制网络节点设计

A Design Method for Control Network Nodes Based on CPLD and Multi-processor Architecture

本文提出了一种新颖的FFT/IFFT处理器结构，并用可编程逻辑器件（CPLD）实现了该结构。

A novel architecture is proposed to implement FFT / IFFT processor with CPLD devices .

为了用于实现多媒体数据处理，针对音视频的DSP处理器结构经过了特别优化设计，且提供了丰富的多媒体处理指令集。

The hardware structure of DSP processor core is especially designed for multimedia data processing , and plentiful multimedia data processing instructions are available .

论文提出了一种基于CPLD和多处理器结构的控制网络节点设计方法。

A design method for control network nodes based on CPLD and multi-processor architecture is proposed in this paper .

一种高级语言（Pascal）控制处理器结构

Architecture of a high level language Pascal control processor

主板采用32位浮点DSP做VXI模块的主板控制器，利用其高度优化的处理器结构和独特的指令系统，对数据采集进行高效实时的控制、分析与处理。

The main board uses a 32-bits floating point DSP to do the real-time control and digital signal processing .

要修改处理器结构则只需编辑核心的makefile并重新运行Linux核心配置程序。

To change architectures you need to edit the kernel makefile and rerun the Linux kernel configuration program .

基于VLIW的并行可配置ECC协处理器结构研究与设计

Architecture research and design of parallel and reconfigurable ECC coprocessor based on VLIW architecture

分析了ARM7TDMI的结构特点，根据处理器结构对MPEG-4编码算法进行了优化。

After analyzing the architecture of ARM7TDMI , MPEG-4 's algorithms are optimized .

数据处理模块采用主从式紧耦合双处理器结构，分别以数字信号处理器（DSP）作为数据处理机，单片微控制器作为I/O接口处理机；

Data processing module with a close-coupled master-slave dual processors employs a digital signal processor ( DSP ) as its data processor and a micro-controller as its I / O interface processor .

本文结合算法研究不同FFT处理器结构的特点，重点研究了流水线结构：MDC和SDF结构。

Features of different FFT processor constructions especially pipeline & MDC and SDF , is studied combined with algorithm .

C、C++和Fortran等基于单指令流和统一存储结构的传统编程模型已经无法适应多核处理器结构。

Traditional programming model like C , C + + and Fortran are poorly suited to multi-core architectures because of the assumed single instruction stream execution model and centralized memory structure .

为了加快签名和验证的速度，给出了一种支持多种椭圆曲线密码（ECC）协议的双核双域ECC处理器结构。

This work presents a dual-core two-field elliptic curve cryptosystem supporting several elliptic curve cryptography ( ECC ) protocols to accelerate signature generation and verification .

结合可扩展的片上互连网络和隐藏延迟的同时多线程结构，论文提出网络互连多线程（NMT，NetworkedMulti-threaded）处理器结构；

Networked multi-threaded ( NMT ) processors are proposed , combined low-latency Network-on-Chip ( NOC ) with Simultaneous Multi-Threading ( SMT ) .

研究了一种基于可重构数据路径的信号处理器结构。其具有功耗低，速度快，灵活性较高等特点，可以做为个人信息处理SoC的核心处理器。

The architecture of a reconfigurable data path DSP with low power , high speed and good flexibility as the center processor of personal information assistant ( PIA ) SoC is investigated .

单片多处理器结构（CMP-ChipMultiprocessor）又是该领域中备受关注的问题。

Single chip multi-processor architecture ( CMP-Chip Multiprocessor ) was hot spots in this area .

系统的硬件设计采用了基于DSP和现场可编程逻辑器件（FPGA）的双处理器结构和基于CMOS的图像采集。

The hardware design of this system is based on a dual-processor architecture which includes a DSP and a Field Programmable Logic Device ( FPGA ), and its image capturing module is based on a CMOS camera .

该评估方法充分考虑了CMOS静态电路的结构级功耗刻画方法，因此更加适合目前以ASIC设计方法为主的高性能处理器结构的功耗评估。

This methodology takes the power modeling methodology of CMOS static circuits into account carefully , so it is better for the estimation of current high performance CPU architecture which is designed with ASIC methodology .

基于神经元芯片和单片机双处理器结构LON节点的研究节能减排的基础技术-功率半导体芯片

Research on LON Node Using Dual Processors Based on Neuron Chip and Microcontroller ; Foundational Technology of Energy-Saving Emission Reduction Power Semiconductor Devices and IC 's

根据智能阀门定位器总线化的要求，开发了基于FF协议的通信接口，阐述了双处理器结构的OEM开发思想，给出了实现FF通信的详细步骤和开发工具。

Aiming at the intelligent valve positioner , the communication interface of the positioner based on FF protocol is exploited in this paper . The OEM development method based on two-CPU structure is expounded .

在介绍了OMAP芯片的双核处理器结构后，阐述了该无线多媒体终端的硬件设计、软件设计，并给出两个示范性多媒体应用实例。

After investigating the advantages of OMAP dual-core architecture , a terminal prototype with software design was constructed . Two multimedia utilities are implemented on the platform were demonstrated .

在剖析NS-2软件的基础上，设计和实现了单总线单处理器结构路由器模拟模块，使仿真网络与现实网络更加一致，完善了该软件面向网络性能评价的功能。

After analyzing NS-2 , a new simulating module of bus-based router with single processor is designed and implemented in NS-2 , which makes the simulating network closer to the real network , and improves the power of network performance evaluation .

具有高效缓冲策略的运动估计阵列处理器结构

Architecture of Processor Array for Motion Estimation with Efficient Cache Scheme

基于总线式、多处理器结构的交通路口控制系统设计

Design of an Intersection Control System Based on Bus & Multiprocessor Structure

支持通用反汇编的处理器结构库设计与实现

Design and implementation of processor structure database for generic disassembly