同步计数器

同步计数器的自启动设计

The Automatic Run Design of the Synchronous Counter

同时介绍一种通用逻辑设计软件&CUPL语言.文中着重介绍了八位二进制可逆同步计数器的功能特点及其用GAL设计的方法。

Then the method of using GAL to design the eight bit binary reversible synchronous counter and a kind of logic design software & CUPL language are also introduced .

用修改法设计N进制同步计数器

Design of mod n sychronous counter using modification method

用CPLD器件实现24位同步计数器的设计

Designing 24 bit in Phase Counter by CPLD

用GAL设计八位二进制可逆同步计数器

The design of eight-bit binary reversible synchronous counter with GAL device

STK空中下载技术中的同步计数器机制研究

Research on Synchronization Counter Mechanism in STK-based OTA Technology

这种计数器称为并行进位同步计数器。

This type of counter is called a parallel-carry synchronous counter .

任意进制同步计数器的优化设计

Optimization of the design of module - N synchronous counter

用D触发器快速设计任意进制同步计数器

Quickly Designing Arbitrary Code Synchronous Counters with D-type Flip flops

逻辑函数修改技术在任意进制同步计数器综合中的应用

Application of Logic Function Modification Technique in the Synthesis of Modulo-N Synchronous Counters

介绍了运用修改法设计同步计数器的方法。

A modification method applied to the design of synchronous counter is introduced .

因上述不等式不能成立，所以不能采用串行进位同步计数器。

Since the above inequality is not satisfied a serial-carry synchronous counter can not be used .

利用这一结果举例设计了有15种指令（T2～T（16））控制的有15种计数周期的同步计数器，并一次完成设计。

Using this result , we have simultaneously completed the design of the synchronous counter with 15 kinds of instructions ( T_2-T_ ( 16 )) and 15 counting periods .

本文给出了该系统对不同的电路形式在不同的器件参数下的模拟结果，为我们的GaAs600门门阵列，四位同步计数器电路等课题的成功研制，发挥了重要的作用。

The simulation results were presented for two circuits with different device parameters . It was proved that this method is helpful in studying and manufacturing the 600 gate GaAs gate-array and 4-bit synchronized count devices .

应用四值逻辑技术讨论异步计数器的分析和设计，给出异步计数器分析和设计的一种方法。这种方法也适用于同步计数器的分析和设计。

This paper discusses analysis and design of asynchronous counters by using four-valued logic techniques and gives methods of analysis and design of asynchronous counters , which can also be used for analysis and design of synchronous counters .

在同步计数器的一般设计方法和同步二进制计数器的连接规律的基础上，提出更简捷、迅速、方便的利用修改法优化设计任意进制同步计数器，并做了举例说明。

On the basis of the ordinary design method of synchronous counter and linking laws of synchronous binary counters , this paper gives a simpler and more direct modification method for optimization of the design of module-N synchronous counter , and elaborates the application of the modification method .

在此基础上提出了使用J-K触发器设计任意进制同步加法计数器、减法计数器和可逆计数器的方法。

Based upon it , the method of design modulo-N synchronous up , down and up / down conters using J-K flip-flops is proposed .

基于电路三要素理论的四值同步可逆计数器设计

Design of four valued synchronous reversible counter based on the theory of three essential circuit elements A

本文推导了任意2n进制循环码计数器的设计公式，并在此基础上分析了2N+1进制同步循环码计数器的构成方法。

In this paper a formula for the design of an arbitrary module-2n counter with cyclic code is suggested . Based on it , the paper analyses a method about how to form the module-2N + 1 synchronous counter with cyclic-code .

2N+1进制同步循环码计数器设计

Design of the Module-2N + 1 Synchronous Counter with Cyclic - Code

本文介绍了一种同步测周期计数器的设计，并基于该计数器设计了一个高精度的数字频率计。

The design of a counter measuring synchronous period is introduced in this paper . And based on it , a high precision digital cymometer is designed .

通过设计实例表明，用此方法设计2N+1进制同步循环码计数器具有使用方便，设计迅速等优点和一定的实用意义。

The designed examples show that the method used to design the module ? N + 1 synchronous counter with cyclic code has the advantages of being easy and fast , and is of certain practical significance .

以同步模4可逆计数器的VHDL语言设计为例，介绍了VHDL和有限状态机的特点以及基于VHDL的有限状态机设计的方法和过程。

Taking VHDL language design of modulo-4 reversible counter as an example , this paper introduces the characteristics of finite state machine and the design method and design process of finite state machine based on VHDL .

同步机制通过同步计数器实现。

Synchronization mechanism is implemented by synchronous counter .