异步计数器

等待异步计数器收集线程结束时超时。

Time out while waiting for asynchronous counter collection thread to end .

在异步计数器设计中，除了无效的状态外，凡是时针脉冲不起作用的时刻，电路的状态也应当成约束项来处理。

On designing a asynchronous counter , not only the uneffective item , but also that the clock pulse unused should be treated as the laced item .

应用四值逻辑技术异步计数器的分析和设计

Analysis and Design of Asynchronous Counters Using Four-Valued Logic Techniques

一种改进的异步计数器分析方法

An Improved Analysis Method for Ripple Counter

本文介绍一种改进的异步计数器分析方法，提出时钟约束状态方程的概念与计算方法；给出了分析步骤与典型实例。

This article introduced an improved analysis methods for ripple counter , put forward the conception and calculating methed of clock restrain state equation , gave the analysis steps and typical examples .

应用四值逻辑技术讨论异步计数器的分析和设计，给出异步计数器分析和设计的一种方法。这种方法也适用于同步计数器的分析和设计。

This paper discusses analysis and design of asynchronous counters by using four-valued logic techniques and gives methods of analysis and design of asynchronous counters , which can also be used for analysis and design of synchronous counters .

为降低系统功耗，本文引入了多种低功耗技术，如系统时钟规划，系统级功耗管理，状态优化编码，全局钟控，异步计数器，门级功耗优化以及操作数隔离等等。

To reduce the power , some low-power techniques are used in this design , such as system clock planning , system level power management , state optimization encoding , global clock gating , asynchronous counter , gate level power optimization , operands isolation , and so on .

异步N进制计数器的简便设计方法

A Simple and Convenient Method to Design Asynchronous N-Scale Counter

介绍了采用FPGA芯片实现揭联惯导系统异步锁存计数器的设计方法，对计数器的性能进行了分析、测试。

The method which adopts FPGA chip to design for asynchronism latching accumulator of SINS is introduced . The accumulator 's performance is analyzed and tested .

本文介绍的异步N进制计数器简便设计方法的原理及其推论，并给出了两个应用实例。

This paper deals with the principles of a simple and convenient method to design asynchronous N - scale counter and the inferences drawn from these principle two practical illustrations are given in the paper .

异步二进制可逆计数器的设计

The asynchronous binary up - down counter of design

异步十进制加法计数器的实验改进

A experimental improvment of asynchronous decimal carry counter

异步任意值计数器的设计

Design of Asynchronous Arbitrary Value Counter

分析了一个异步十进制加法计数器实验电路的错误，介绍了异步十进制加法计数器典型电路。

This paper analysis the errors of experimental circuit on a asynchronous decimal carry counter , introduces a typical circuit on a asynchronous decimal carry counter .