行为级

本文分别从行为级和RTL级实现并且验证了DES电路。

Grade . We implement and verify the DES circuit on behavior level and Register Transfer Level ( RTL ) .

基于RTOS的嵌入式软件验证方法以编译代码模型为基础，从系统行为级验证嵌入式软件功能，验证速度快。

The simulating method based on the compiled code model for the embedded software verifies the software from the system behavior level , so higher co-verification performance can be achieved .

基于Matlab的△∑调制器的行为级建模与仿真

Behavioral Modeling and Simulation of ΔΣ Modulator Based on Matlab

一种精确的锁相环IP模块行为级建模

Accurate IP Behavioral Modeling of Phase Lock Loop

基于Matlab流水线A/D转换器行为级模型建模与仿真

Behavioral Modeling and Simulation of Pipeline ADC Using Matlab

行为级DSP算法描述的阵列处理器综合方法研究

High Level Array Processors Synthesis of Digital Signal Processing

SYSTEMC语言是一种建立在C++之上的可以在行为级描述系统功能的仿真建模语言。

System C language is based on C + + language . With System C , we can describe the behaviors of a system and realize a system simulation .

SOC的设计不断向更高层次的设计方法发展，设计者比以往更加关注系统级、行为级和RTL的设计。

The SOC design method has moved to higher level now .

锁相环行为级建模及在视频行锁相中的应用基于FPGA的三相锁相环的优化设计方案

Behavior Modeling of PLL and Its Application in Video Horizontal PLL Optimized implementation scheme of three phase phase-locked loop based on FPGA

然后，在Matlab环境下对二阶Sigma-Delta调制器进行了行为级仿真，确定了电路设计所需的关键指标。

Then , the behavior simulation was performed on a 2nd-order Sigma-Delta modulator under Matlab .

并通过与SPICE模拟结果的比较，对所提出的行为级模型的精度进行了验证。

The accuracy of the proposed models is verified by comparison with SPICE simulation results .

基于Verilog-A的sigmadelta系统行为级建模

Sigma Delta Modulators Behavioral Modeling Based on Verilog-A

有效的ASIP行为级设计方法对于SoC设计具有重大意义。

An efficient ASIP behavior-level design method plays an important role in SoC design .

混合信号硬件描述语言（MS-HDL，Mixed-SignalHardwareDescriptionLanguage）的出现，使混合电路的行为级描述成为可能。

The presence of the mixed-signal hardware description language ( MS-HDL ) makes the behavioral description of mixed signal circuits feasibly .

本文对一种改善ADC非线性误差的数字校准算法进行了研究。在Matlab中进行了行为级仿真，评估了这种方法对增益非线性误差的校准效果。

A digital calibration algorithm is studied in this paper , the behavioral simulation is done by matlab , and the evaluation results are showed .

采用主-分的树状控制模式，结合模块化的控制理念，通过SPI总线方式对各模块进行行为级的控制。

The system employed tree structure with the modular design concept , and controlled each module behaviorally by SPI bus .

基于Verilog-AMS的DC-DC变换器行为级稳定性设计

The Behavioral Level Stability Design of DC-DC Converter with Verilog-AMS

基于Verilog-A行为级模型的三阶单环调制器设计与仿真

Third-Order Single-Loop Sigma-Delta Modulator Design and Simulation Based on Verilog-A Behavioral Model

高层次综合也叫行为级综合，其基本任务是完成数字系统行为描述到寄存器传输级（RTL）描述的转换。

The main task is translating the behavioral description of a digital system into the design of RTL ( Register Transfer Level ) .

完成了TFT-LCD驱动芯片电源电路中内置电荷泵升压／反压电路的设计，并采用Verilog-A行为级模型和SPICE网表相结合的混合仿真方法完成了电荷泵电路的验证。

Voltage step-up and inversion circuit built-in TFT-LCD driver IC are designed and also verified by mixed-simulation using Verilog-A behavior model and SPICE netlist .

在行为级综合中，一般在调度与分配之前先将系统的描述转换成一个数据流程图（DFG）。

In behavior synthesis , the behavior of the system is always transformed to a DFG before scheduling and allocation .

此模型考虑了功率MOSFET必要的二阶效应，并采用行为级模型来处理JFET电阻。

The 2nd-order effect necessary for power MOSFET 's was taken into account in the macro-model and behavioral model was used to deal with JFET resistance .

提出采用一种规范化的香农小波（distributedapproximationfunction，SGWD）逼近算法建立模拟电路单元模块的行为级模型。

In this paper , Shannon-Gabor wavelet distributed approximation functions ( SGWD ), which combine Shannon sampling with a Gabor-distributed approximation functional ( Gabor-DAF ) window function , are used to construct the behavioral models of analog circuit blocks .

二维离散小波变换结构已经过VHDL行为级仿真验证，并可作为单独的JPEG2000IP核应用于各种实时图像/视频芯片中。

The architecture had been implemented and simulated in behavioral VHDL . The architecture could be used as a compact and independent IP core for JPEG 2000 VLSI implementation and various real-time image / video applications .

但由于其功能强大，可以完成各种以太网的行为级模拟。导致其控制非常复杂。在工程应用中，验证工程师不得不学习大量的BFM文档，这会大大降低工程师的工作效率。

Because of its powerful function , it could finish all kinds of Ethernet behavior level simulation , it is very complex to use .

分析了模拟硬件描述语言Verilog-A的特点，介绍了基于Verilog-A语言的行为级模拟电路设计过程。

The characteristics of Verilog-A HDL are introduced and the flow of system level simulation using Verilog-A behavioral model is analyzed .

设计了锁相环电路的鉴频鉴相器（PFD）单元、电荷泵（CP）单元、环路滤波器（LF）单元、压控振荡器（VCO）单元和一些辅助功能电路的行为级模型。

The behavioral level models of CPPLL include such sub modules : phase frequency detector ( PFD ), charge pump ( CP ), loop filter ( LF ), voltage control oscillator ( OSC ) and some auxiliary circuits .

结合实际需求，分析了多种仿真模型的工作原理及各自的适用范围，并选用IBIS模型进行行为级仿真。

Combined with the actual demand , a variety of simulation models and their respective scope of application are introduced , and the IBIS model is selected to process the behavior level simulation .

结果表明，使用Verilog-AMS语言对模拟部分进行行为级建模能够在很大程度上减少仿真所需要的时间，加快设计进程，并且提高仿真精度。

The simulation result shows that the behavioral model of Verilog-AMS will shorten the time of simulation and improve the precision of simulation .

围绕数字式LVDS接口整合式LCD控制器的设计，本文进行了行为级、RTL级、电路级设计与验证，并给出了系统的后端设计：可测性设计、低功耗设计及版图的设计与验证。

Around the design of the integrated LCD controller with LVDS transmitter , this thesis process behavior , RTL , circuit level verifications , and system back-end design , including DFT , low power design and layout design and verification .