环路滤波器

一种采用N先于M环路滤波器的全数字锁相环路的设计实现

The Design and Realization of a Kind of DPLL Using a N before M Loop Filter

系统中的环路滤波器采用RC积分滤波器，鉴相器采用三角形鉴相特性；

In this systems , loop filter is RC integral filter and phase-detector is triangle phase-detector characteristic .

AVS解码器帧内预测和环路滤波器硬件设计与实现

Design and Implementation of Intra Prediction and Loop Filter in AVS Video Decoder

Fuzzy逻辑控制器与环路滤波器一起构成的智能环路滤波器能够根据环境的变化动态调整环路带宽，同时解决了跟踪速度和跟踪精度的矛盾。

The intelligent filter which is made up of Fuzzy logic controller and loop filter can dynamically verify loop bandwidth . Therefore , the contradiction between the tracking speed and precision is solved .

AVS环路滤波器设计及实现

Design and implementation of an AVS loop filter

环路滤波器（LoopFilter，简称LPF）是锁相环（PLL）的重要组成单元，它在很大程度上决定了PLL的性能。

The Loop Filter , being the important part of any PLL based frequency synthesizer , its performance determines to a large extent that of the whole synthesizer .

锁相环采用二阶的模拟锁相环结构，鉴相器采用Gilbert乘法器，环路滤波器采用无源滤波器，VCO采用3级环形振荡器。

The analog PLL contains three basic components : a Gilbert multiplier PD , a passive filter and a three-stage ring oscillator .

FSK电路关键是电荷泵PLL芯片、VCO电路和环路滤波器的参数计算和仿真优化。

The key of the FSK design is the calculation , simulation and optimization of the charge pump PLL chip , VCO and loop filter .

最后，基于UMC0.13μMRFCMOS工艺完成了应用于小数型频率合成器的电荷泵和环路滤波器单元的设计、仿真、优化与验证。

At last , the design , simulation , optimize and verification of charge pump and loop filter for fractional-N frequency synthesizer have been accomplished , based on UMC 0.13 μ m RF CMOS process .

传统的AFC采用了模拟环路滤波器，因此只能工作在连续的输入信号模式，而不能工作于间断导频的WCDMA系统中。

A traditional AFC adopts analog loop filter that must work consecutively . However , in W CDMA system , the pilot parts are discontinuous . A novel digital approach of AFC is presented .

环路滤波器的作用就是滤除从PFD&CP出来的电压中的高频成分，从而纯化VCO的输出信号。

The function of a loop filter is to filter high-frequency signal out of the output voltage from PFD and CP , thus the output signal from VCO will be purified .

以常用2阶PLL（使用1阶RC无源环路滤波器）为基础，作者首次就PLL的动态跟踪特性及其对同步测量精度的影响问题进行了详细的分析和仿真。

Based on the second order PLL , which uses a first order RC filter as loop filter , the characteristic of dynamic tracking of PLL and its influence on the accuracy of synchronized measurement are analyzed and simulated .

针对电流型电荷泵PLL频率综合器芯片，提出一种称为极值相位裕量的无源环路滤波器方案和设计方法。

A passive loop filter scheme and the design method of the filter for current charge pump PLL frequency synthesizer chip are given in the paper . The method is known as the method of extreme value phase margin .

设计了锁相环电路的鉴频鉴相器（PFD）单元、电荷泵（CP）单元、环路滤波器（LF）单元、压控振荡器（VCO）单元和一些辅助功能电路的行为级模型。

The behavioral level models of CPPLL include such sub modules : phase frequency detector ( PFD ), charge pump ( CP ), loop filter ( LF ), voltage control oscillator ( OSC ) and some auxiliary circuits .

本文介绍了锁相环PLL电路的设计与应用，内容包括PLL工作原理与电路构成，PLL电路的传输特性，PLL电路中环路滤波器的设计方法，PLL特性改善技术及频率DDS合成技术。

This article describes the phase-locked loop PLL circuit design and application , including working principle and PLL circuits , PLL circuit transmission characteristics , PLL loop filter circuit design , PLL frequency of DDS technology and features to improve the synthesis .

本文建议在分析复杂锁相环时，把压控振荡器（VCO）和环路滤波器之外的所有其它部件等效地看成是一个鉴相器。

This paper suggests that in the analysis of the complex phase locked loops all the components of a phase locked loop be treated , equivalently as a phase discriminator except the voltage controlled oscillator and the loop filter .

完成了锁相频率源有源电路各个功能单元模块的设计，包括：三个锁相环电路及其DDS电路、有源环路滤波器电路和电源电路等。

A microwave calibration signal is generated by a down-converter in the third loop . ( 2 ) Active circuits design for the proposed frequency synthesizer is accomplished , including : three PLL and DDS circuit , an active loop filter circuit and power-supply circuit .

介绍了在高级准同步数字体系（APDH）中的2MBs接口的数字环路滤波器的改良方案。

This paper discussed the improvement of a digital loop filter of 2Mb / s interface in APDH ( Advanced PDH ) .

主要讨论了低相位噪声微波锁相频率合成器的设计，并对影响其相位噪声的主要因素如环路滤波器、分频器、鉴相器及压控振荡器（VCO）分别作了分析和讨论；

This paper discusses the design of phase-locking frequency synthesis oscillator with low phase noise , and analyses and discusses the main causes for its phase noise such as loop filter , frequency divider , phase discriminator and voltage control oscillator ( VCO ) .

过零锁相即硬件锁相（PLL）由鉴相器、环路滤波器、压控振荡器及分频器组成，其原理和结构较简单，但动态性能较差，且在畸变电压输入时锁相效果变差；

The zero-crossing PLL i.e.hardware PLL , is comprised of PFD ( Phase-Frequency Detector ), loop filter , VCO ( Voltage Control Oscillator ) and frequency divider . It is really simple but poor in dynamic performance , and even worse in phase lock effect with distorted input voltage .

在此基础上，本文采用硬件描述语言在Altera公司QuartusⅡ开发环境下设计了QPSK调制解调器，详细介绍了数字控制振荡器、成形滤波器、环路滤波器和位同步模块的设计过程。

On this basis , QPSK modulator and demodulator are designed using HDL ( hardware description language ) in Altera Quartus ⅱ software . The design of NCO , shaping filter , Loop Filter and bit synchronization is illuminated in detail .

误差分离双通道环路滤波器的分析与设计

Analysis and Design of Double Channel Filter for Loop Error Separating

低相噪、低杂波数字锁相环路滤波器的设计

Low Phase Noise and Spurious Digit PLL ′ s Loop Filter Design

用仿真手段对这两种不同的环路滤波器进行了仿真，清楚地表明了电阻对相位噪声的影响。

Simulation for these loop filters shows resistors ' contribution to phase noise .

软件锁相环环路滤波器和闭环幅频响应分析

Analysis of the Magnitude Frequency Responses of Software Phase-Locked Loop and Its Loop Filter

频率合成器环路滤波器的设计

Design of Frequency Synthesizer 's Loop Filter

激光通信数字环时隙同步器环路滤波器设计

The Loop Filter in Digital Phase Locked Loop Time Slot Synchronizer for Underwater Laser Communication

全数字化的电子光学锁相、尤其是数字环路滤波器在电子光学锁相环中的实现在国际上尚属首次，暂无同类报道。

All digital optical phase locking loop is implemented for the first time in the world .

提出了一种隐式双路径环路滤波器结构。该结构克服了传统双路径滤波器需要两个电荷泵的缺点。

An implicit dual-path loop filter is proposed , which is driven by a single charge pump .

本文讨论的全数字锁相环包括过零检测器和环路滤波器。

This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter .