存储器地址

存储器地址线断路故障的检测方法

Diagnosis Way of Broken Fault of Memory Address Line

地址路径选择指示符存储器地址选择寄存器

Address routing indicator memory address select register

解决了在DSP提供的地址线少于异步存储器地址线的情况下，实现并行加载的问题。

The parallel booting problem , which occurs when the number of the address lines provided by DSP is less than that of the asynchronous memory , is also solved .

提出了一种支持多标准视频的存储器地址映射方法，用一个简洁的公式把视频图像映射到DDRSDRAM的存储空间。

In this paper , an address mapping method for multi-standard video is presented , which maps video picture into the memory space of DDR SDRAM with a simple formula .

在访问主存前，必须将虚拟存储器地址转换为实际存储器地址。

The virtual memory addresses must be translated into actual memory addresses before main memory is referenced .

处理机本机存储器地址寄存器

Processor local storage address register

相对编码中，在某一区域内寻址时所参照的绝对存储器地址。

In relative coding , the absolute storage address to which addresses in a region are referenced .

关于8031单片机扩展多片外部程序存储器地址问题的探讨

The single chip microcomputer of 8031 can be extended the multichip external program memory address : discussion

虚拟存储器地址转换

Virtual memory address translation

存储器地址选择寄存器

Memory address select register

实验存储器地址寄存器

Experimental memory address register

地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。

The address bus is used by the processor to select aspecific memory location or register within a particular peripheral .

因此在分块并行译码方案中要解决的一个关键问题就是设计出能够避免存储器地址争用问题的碰撞自由交织器。

A challenge in the design of parallel Turbo decoder is the design of collision-free interleavers in order to avoid the memory access collision .

数据采集系统触发电路、随机采样短时间产生电路、存储器地址计数器电路等相关控制电路的设计、仿真和调试；

The circuits revelent to data acquisition system such as trigger circuit , the circuit of short time generator in random sampling etc , are designed , simulated and adjusted .

对m序列与存储器地址线非顺序连接的情形、地址线位数与量化噪声功率、截幅噪声功率及输出信号的自相关函数的关系进行了理论分析。

And gives an theory analysis of the bonded case between m-seriation and negate sequential connection of memory address line , order of units of address line and noise power of quantization , noise power of sever amplitude and self-correlation function of signal waveform .

CMOS存储器中地址译码器的开路故障及测试

Open Defects and Testing in CMOS RAM Address Decoders

主要包括规划存储器的地址空间、配置硬件设备、改良Flash驱动程序。

These functions include arrangement of address space , configuration of hardware and improvement of Flash driver .

主要论述了MCS-51系列单片机程序存储器超地址空间的扩展问题，给出了一种具体的扩展方法，并对相关问题进行了探讨。

This paper discusses mainly the problem of extra-address space extending for pro-gram memory in MCS-51.It gives a specific extending method , and probes into the related problems .

本文还对存储器的地址生成算法进行了详细的讨论。

An effective address generation algorithm for this design was proposed in detail too .

局部存储器的地址寄存器

Local storge address register addressable memory

存储器缓冲地址寄存器

Memory buffer address register

访问未映象到虚拟存储器的地址，或是访问当前存取方式无法访问的地址。

An attempt to reference an address that is either not mapped into virtual memory or not accessible by the current access mode .

提出了一种利用大容量FLASH存储器存放楼层地址信息的汉字火灾楼层显示器。

A Chinese fire indicator which used a large-capacity FLASH for floor address information is proposed .

当CPU读取Cache的数据时，先将物理地址的最高位与标志存储器中对应地址标签比较。判断是否将数据总线直接传送给CPU。

When CPU read Cache data , it compared the highest position of physical address with corresponding address label of symbol memory at first to determine whether the data in cache memory should be sent to CPU directly .

PPE用载入和存储指令访问主存储器（有效地址空间），可以在主存储器与内容可以缓存的私有寄存器文件之间移动数据。

The PPE accesses main storage ( the effective-address space ) with load and store instructions that move data between main storage and a private register file , the contents of which may be cached .

由于Windows9X系统的内存管理采用水平存储模式（FLATMemoryModel），其线性地址空间和物理地址空间是分离的，使得在应用程序中无法直接得到存储器的物理地址。

The Flat Memory model that separate the linear space from physical space is introduced to the memory management system in Windows 9x so that the physical address of memory can not be accessed directly .

存储器位置，地址，编址指定于某个特定区域内，用于信息存储或提取的数字

A number used in information storage or retrieval that is assigned to a specific memory location

所以本系统主要包括多通道开关、峰值保持、高速A/D、帧存储器、内地址发生器和时序及逻辑控制等几部分。

Therefore the data acquisition system includes mainly a multiple channel switch , a peak value holding circuit , a high speed A / D converter , a frame memory , an address generator , a sequence and logic control circuit .

可编程逻辑器件CPLD完成对整个系统的逻辑控制以及提供存储器写数据的地址。

The CPLD is used to control the logic of whole system , and it also provides the write address of memory .

在任何情况下指令存储器所对应的地址空间都是可缓存的。

The address space corresponding to instruction memory is always indicated cacheable , which is correct in function .