存储器带宽

由于受到存储器带宽的限制，目前宽带路由器一般采用输入缓冲的crossbar交换开关。

Limited by memory bandwidth , high bandwidth routers often use input queued crossbar switch fabric .

在信号处理、高性能网络设备和高清音视频等领域，尤其对于多核SoC设计，存储器带宽越来越成为限制系统性能的瓶颈。

In the field of signal processing , high efficiency network , and high definition audio / video , memory bandwidth has increasingly become a bottleneck , especially in multi-core SoC designs .

由于在目前存储器带宽的限制下，输入缓冲crossbar交换开关比传统的共享存储交换开关能提供更大的交换能力，因此这类开关已经在新一代的核心路由器中广泛使用。

Under the limitation of memory access speed , input-buffered crossbar can provide more bandwidth than the traditional share-memory switch .

目前的GPU已经具备了很好的可编程能力，并发展成为一种高并行、多核、多线程的处理器，其计算功率和存储器带宽相较于CPU有着杰出的优势。

Now the GPU already has good programmability . It has evolved into a highly parallel , multi-core , multi-threaded processor . Comparing with CPUs , GPUs have outstanding advantage in computing power and memory bandwidth .

它不仅可以提高存储器带宽，而且可以减少存储器资源。

It can increase memory bandwidth and reduce the memory resources .

对提高高速数据采集系统的采样率和存储器带宽这两大技术难题提出了补救措施。

The compensating measure is put forward to solve the two technological problems of sampling and memory bandwidth enhancement of high speed data acquisition systems .

本文第四章从提高存储器带宽利用率的角度出发，考虑到环路去块滤波和帧内预测模块的数据相关性，提出了一种更加有效的存储空间优化策略。

To lower the frequency of data scheduling , a more efficient memory allocation strategy , in which the data correlation of intra prediction and in-loop de-blocking filtering is considered deliberately , is proposed in the chapter 4 .

单路径延迟反馈流水结构的设计提高了计算速度，降低了对于外部存储器数据带宽的限制，有效控制了芯片引脚。

Single-path delay feedback pipeline can improve the processing speed and lower the restriction of the external memory data bandwidth with favorable chip pins .

提出了一种新的存储器结构&多倍带宽存储器结构（MBM）。

This paper presents a new memory architecture , multiple bandwidth memory architecture .

提出一种新型的三级存储阵列结构可以成功解决数据包存储器的容量和带宽问题，理论上可以实现任意高速数据包的缓存。

This paper presents a tri-stage memory array architecture to solve the problem , which can accomplish the arbitrary high-speed packet buffer theoretically .

充分利用CPU多条数据总线并行访问多个存储器块的能力和双端口存储器（DARAM）一个周期两次访问的能力，减小存储器带宽的限制。

Parallel access to multiple memory banks by several data buses and dual access through dual Access Random Access Memory ( DARAM ) reduces the memory bandwidth limit .