静态功耗
- 网络Static power dissipation;Static Power;static current
![静态功耗](../cache/1399460.jpg)
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CMOS集成电路功耗的物理来源主要有两种:由于CMOS管工作状态变化而引起的动态功耗和由于漏电流而产生的静态功耗。
It has two main source of power dissipation for CMOS integrated circuits : the dynamic power dissipation , which is caused by the change of CMOS transistor working state , and the static power dissipation , which is caused by the leaking current .
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一种低静态功耗的CMOS集成稳压器的实现
Implementation of a Low Static Power Dissipation of CMOS Integrated regulator
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静态功耗是CCD片上输出放大器所消耗的功率;
Static power is dissipated in the on-chip output amplifier .
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利用遗传算法实现CMOS组合电路静态功耗优化
CMOS Combinational Circuit Leakage Power Reduction Using Genetic Algorithms
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双阈值CMOS电路静态功耗优化
Optimization of Static Power for Dual Threshold CMOS Circuits
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CMOS电路动静态功耗协同分析
Dynamic and Static Power Co-analysis of CMOS Circuits
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在0.35μMCMOS工艺模型下,该缓冲放大器的静态功耗为60μW。
Based on 0.35 μ m CMOS process , the quiescent power of this buffer amplifier is 60 μ W.
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在70Gy下,静态功耗电流增加4.5个量级。
The statical power current increases by 4.5 order of magnitude .
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该结构通过门控Gnd技术来动态地关闭或开启部分cache路,使得cache结构可以在低功耗配置和正常配置之间切换,从而达到降低静态功耗的目的。
This novel cache architecture can turn off some unused ways and run in configuration with low power , otherwise it runs in normal configuration , so it can reduce the average leakage power .
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其次根据电路处于待机或空闲模式时,静态功耗的大小与电路所处的状态有关的特点,提出了基于遗传算法(GA)的CMOS电路泄漏功耗估计方法。
Secondly , a leakage power estimation method based on GA ( genetic algorithm ) was proposed for CMOS circuits according to the static power dissipation depend upon the state of circuits when they worked in standby or idle mode .
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该模型可用于CMOS组合电路静态功耗估算和优化.面向基于标准单元的CMOS组合电路,利用输入向量控制技术,采用遗传算法作为求解手段,建立了CMOS组合电路静态功耗优化环境。
A VSF-based leakage power evaluation model is then developed and used for evaluating and reducing the leakage power of CMOS combinational circuits . A leakage power reduction platform for CMOS combinational circuits by means of input vector control is presented .
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并对不同型号的PTC启动器动作时间之间、恢复时间之间、静态功耗之间及常温电阻间的数据进行比较,以得到影响PTC综合参数的电学因素。
And different types of PTC starter operating time between the recovery time between the static power consumption and temperature resistance between the comparison of data between , to get the PTC synthesis parameters affecting the electrical factors .
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其中,设计了一个新颖的多数投票器电路结构,具有速度快、动态功耗低和零静态功耗的优点,对降低BI空间编码器引入的能耗和延时开销具有重要作用。
This technique has a highlight that the BI spatial encoder is based on a novel majority voter circuit with desirable merits such as high-speed , low-power operation and near-zero static power , thereby , resulting in significantly reduced energy and delay overhead of spatial encoder .
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SRAM的功耗可分为静态功耗和动态功耗,工作在亚阈值区域的SRAM存储单元功耗很低但其稳定性也更容易受到工艺、电源电压及温度(PVT)的影响。
The power consumption of SRAM can be divided into static and dynamic power consumption ; SRAM memory cells which works in the sub-threshold area have a very low power consumption but their stability is also more susceptible to process , supply voltage and temperature ( FVT ) .
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基于CMOS0.35工艺,用SPECTRE对该电路进行仿真,改进后的电路可消除1.2mA的注入电流,稳定工作在25/12.5MHz下,其最低工作电压为2.2V,静态功耗为0.44mA,达到设计目标。
The circuit is simulated by SPECTRE using CMOS 0.35 μ m process and the satisfied result is achieved , which eliminates 1.2 mA injection current and operates stably under 25 / 12.5 MHz with 2.2 V of the lowest voltage , 0.44 mW of static power consumption .
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VSF:CMOS组合电路的静态功耗评估模型
VSF : A Leakage Power Evaluation Model for CMOS Combinational Circuits
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附加静态功耗电流与系统设计者的关系
The Importance of Additional Quiescent Current ( Icc △) for System Designer
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深亚微米集成电路静态功耗的优化
Optimization of Standby Power in Deep Sub - micron Integrated Circuit s
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设计了级恢复电路,解决了导通晶体管开关引起的静态功耗问题。
A level - restoring circuit was designed to solve the static power dissipation problem .
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在遗传算法中利用电路状态差异度作为适应度函数,求解使电路静态功耗最小的输入向量。
Genetic algorithm is used for searching minimum leakage vector and circuit status difference is used as fitness function .
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接下来具体分析了功耗的组成以及动态功耗和静态功耗的优化方法。
The second it detailed analysis of the composition of power , and dynamic power and static power optimization method .
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这就给适时关闭空转的部件,降低时钟动态功耗和静态功耗提供了很大的空间。
This leaves a large space for turning off idle units properly and saving clock dynamic power consumption and static power consumption .
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随着工艺的发展,器件阈值电压的降低,导致静态功耗呈指数形式增长。
As technology evolves , the threshold voltage will be re-duced accordingly , which results in an exponential increase of standby power .
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在开发新的低漏流工艺和电路技术之外,如何在体系结构级控制和优化静态功耗成为业界研究的热点。
Beside developing low leakage technologies and circuits , how to control the static power at the architectural level is worth being studied .
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通过该方法,能够找出电路处于待机或空闲模式时产生静态功耗最低的输入向量。
By it , the input vectors that produce the minimum leakage power could be searched out when circuit worked in standby or idle mode .
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本文设计了一种基于堆栈效应的漏电流模拟器,并提出了通过该模拟器,利用测试向量中特有的不确定位以优化测试中静态功耗的方法。
Using the simulator , we give a method based on the don t care bits in the test vectors to optimize the static test power .
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在设计中,本文仔细考察了指令的并行性,并以此为根据设计了相应的硬件并行使用规则和硬件复用方案,可以有效降低系统的静态功耗。
We design the reusing-hardware and the rules for parallel use of the hardware by instructions , which are all based on ingenerate ILPs of the instruction set .
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在标志位控制下,用来存放超窄数据的高存储单元将被关闭,以节省其动态和静态功耗。
At the control of an additional flag bit , the higher bits of the data cells that store VNV are closed to save its dynamic and static power consumption .
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提出一种低功耗准动态移位寄存器电路,这种电路静态功耗几乎为0,仅仅存在动态功耗;
In this paper a new low-power quasi-dynamic shift register is presented . It is of low power dissipation near to 0 for the static power and has only dynamic power .
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同时根据产品对低功耗的应用要求,芯片内部集成了信号丢失检测模块,其可根据使用环境关断开启输出缓冲单元,能够有效降低限幅放大器的静态功耗。
Meanwhile , a signal loss detection module is integrated into the chip for low-power applications . The module can close or open output buffer to effectively reduce the static power consumption .